Freescale Semiconductor MPC8313E Family Reference Manual page 50

Figure
Number
15-62 Receive FCS Error Counter Register Definition................................................................. 15-84
15-63 Receive Multicast Packet Counter Register Definition ...................................................... 15-85
15-64 Receive Broadcast Packet Counter Register Definition ..................................................... 15-85
15-65 Receive Control Frame Packet Counter Register Definition .............................................. 15-86
15-66 Receive Pause Frame Packet Counter Register Definition ................................................. 15-86
15-67 Receive Unknown OPCode Packet Counter Register Definition ....................................... 15-87
15-68 Receive Alignment Error Counter Register Definition....................................................... 15-87
15-69 Receive Frame Length Error Counter Register Definition ................................................. 15-88
15-70 Receive Code Error Counter Register Definition ............................................................... 15-88
15-71 Receive Carrier Sense Error Counter Register Definition .................................................. 15-89
15-72 Receive Undersize Packet Counter Register Definition ..................................................... 15-89
15-73 Receive Oversize Packet Counter Register Definition ....................................................... 15-90
15-74 Receive Fragments Counter Register Definition ................................................................ 15-90
15-75 Receive Jabber Counter Register Definition....................................................................... 15-91
15-76 Receive Dropped Packet Counter Register Definition ....................................................... 15-91
15-77 Transmit Byte Counter Register Definition ........................................................................ 15-92
15-78 Transmit Packet Counter Register Definition ..................................................................... 15-92
15-79 Transmit Multicast Packet Counter Register Definition ..................................................... 15-93
15-80 Transmit Broadcast Packet Counter Register Definition .................................................... 15-93
15-81 Transmit Pause Control Frame Counter Register Definition .............................................. 15-94
15-82 Transmit Deferral Packet Counter Register Definition....................................................... 15-94
15-83 Transmit Excessive Deferral Packet Counter Register Definition...................................... 15-95
15-84 Transmit Single Collision Packet Counter Register Definition .......................................... 15-95
15-85 Transmit Multiple Collision Packet Counter Register Definition....................................... 15-96
15-86 Transmit Late Collision Packet Counter Register Definition ............................................. 15-96
15-87 Transmit Excessive Collision Packet Counter Register Definition .................................... 15-97
15-88 Transmit Total Collision Counter Register Definition ........................................................ 15-97
15-89 Transmit Drop Frame Counter Register Definition ............................................................ 15-98
15-90 Transmit Jabber Frame Counter Register Definition .......................................................... 15-98
15-91 Transmit FCS Error Counter Register Definition ............................................................... 15-99
15-92 Transmit Control Frame Counter Register Definition ........................................................ 15-99
15-93 Transmit Oversized Frame Counter Register Definition .................................................. 15-100
15-94 Transmit Undersize Frame Counter Register Definition .................................................. 15-100
15-95 Transmit Fragment Counter Register Definition .............................................................. 15-101
15-96 Carry Register 1 (CAR1) Register Definition................................................................... 15-101
15-97 Carry Register 2 (CAR2) Register Definition................................................................... 15-103
15-98 Carry Mask Register 1 (CAM1) Register Definition........................................................ 15-104
15-99 Carry Mask Register 2 (CAM2) Register Definition........................................................ 15-105
15-100 Receive Filer Rejected Packet Counter Register Definition ............................................. 15-106
15-101 IGADDRn Register Definition ......................................................................................... 15-107
15-102 GADDRn Register Definition........................................................................................... 15-108
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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Freescale Semiconductor