Memory Refresh Timer Prescaler Register (Mrtpr); Upm/Fcm Data Register (Mdr) - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Local Bus Controller
Bits Name
18–21 WLF Write loop field. Determines the number of times a loop defined in the UPM n will be executed for a burst- or
single-beat write pattern.
0000 16
0001 1
0010 2
0011 3
...
1110 14
1111 15
Refresh loop field. Determines the number of times a loop defined in the UPM n will be executed for a refresh
22–25 TLF
service pattern.
0000 16
0001 1
0010 2
0011 3
...
1110 14
1111 15
26–31 MAD Machine address. RAM address pointer for the command executed. This field is incremented by 1, each time
the UPM is accessed and the OP field is set to WRITE or READ. Address range is 64 words per UPM n .
10.3.1.5

Memory Refresh Timer Prescaler Register (MRTPR)

The refresh timer prescaler register (MRTPR), shown in
twice csb_clk (if RCWL[LBCM] is set) to provide the UPM refresh timers clock.
Offset 0x084
0
R
PTP
W
Reset
Figure 10-8. Memory Refresh Timer Prescaler Register (MRTPR)
Table 10-12 describes MRTPR fields.
Bits Name
0–7 PTP Refresh timers prescaler. Determines the period of the refresh timers input clock. The csb clock (or twice
csb_clk (if RCWL[LBCM] is set) is divided by PTP except when the value is 00000_0000, which represents
the maximum divider of 256.
8–31 — Reserved
10.3.1.6

UPM/FCM Data Register (MDR)

The memory data register (MDR), shown in
from the RAM array for UPM read or write commands. MDR also contains data written to or read from
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
10-22
Table 10-11. M x MR Field Descriptions (continued)
7 8
Table 10-12. MRTPR Field Descriptions
Figure 10-9
Description
Figure 10-8, is used to divide the csbclock (or
—
All zeros
Description
and Figure 10-10, contains data written to or read
Access: Read/Write
31
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