Freescale Semiconductor MPC8313E Family Reference Manual page 877

Enhanced Three-Speed Ethernet Controllers
TSECn_RX_DV is asserted and as long as TSECn_COL remains negated (full-duplex mode ignores
TSECn_COL), the MAC looks for the start of a frame by searching for a valid preamble/SFD (start of
frame delimiter) header, which is stripped (unless MACCFG2[PreAM RxEN] is set) and the frame begins
to be processed. If a valid header is not found, the frame is ignored.
If the receiver detects the first bytes of a frame, the eTSEC controller begins to perform the frame
recognition function through destination address (DA) recognition (see Section 15.6.2.7, "Frame
Recognition"). Based on this match the frame can be accepted or rejected. The receiver can filter frames
based on individual (unicast), group (multicast), and broadcast addresses. Because Ethernet receive frame
data is not written to memory until the internal frame recognition algorithm is complete, system bus usage
is not wasted on frames unwanted by this station.
If a frame is accepted, the Ethernet controller fetches the receive buffer descriptor (RxBD) from either
queue 0 or the queue determined by the filer. If the RxBD is not being used by software (RxBD[E] is set),
the eTSEC starts transferring the incoming frame. RxBD[F] is set for the first RxBD used for any
particular receive frame. If the current RxBD is not available for the received frame, a receive busy error
condition is raised in IEVENT[BSY].
After the buffer is filled, the eTSEC clears RxBD[E] and, if RxBD[I] is set, generates an interrupt. If the
incoming frame is larger than the buffer, the Ethernet controller fetches the next RxBD in the table. If it is
empty, the controller continues receiving the rest of the frame. In half-duplex mode, if a collision is
detected during the frame, no RxBDs are used; thus, no collision frames are presented to the user except
late collisions, which indicate LAN problems.
The RxBD length is determined by the MRBL field in the maximum receive buffer length register
(MRBLR). The smallest valid value is 64 bytes, with larger values being be some integral multiple of 64
bytes. During reception, the Ethernet controller checks for frames that are too short or too long. After the
frame ends (CRS is negated), the receive CRC field is checked and written to the data buffer. The data
length written to the last RxBD in the Ethernet frame is the length of the entire frame, which enables the
software to recognize an oversized frame condition.
Receive frames are not truncated when they exceed maximum frame bytes in the MAC's maximum frame
register if MACCFG2[Huge Frame] is set, yet the babbling receiver error interrupt occurs
(IEVENT[BABR] is set) and RxBD[LG] is set.
After the receive frame is complete, the Ethernet controller sets RxBD[L], updates the frame status bits in
the RxBD, and clears RxBD[E]. If RxBD[I] is set, the Ethernet controller next generates an interrupt (that
can be masked) indicating that a frame was received and is in memory. The Ethernet controller then waits
for a new frame.
To interrupt reception or rearrange the receive queue, DMACTRL[GRS] must be set. If this bit is set, the
eTSEC receiver performs a graceful receive stop. The Ethernet controller stops immediately if no frames
are being received or continues receiving until the current frame either finishes or an error condition
occurs. The IEVENT[GRSC] interrupt event is signaled after the graceful receive stop operation is
completed. While in this mode the user can write to registers that are accessible to both the user and the
eTSEC hardware without fear of conflict, and finally clear IEVENT[GRSC]. After DMACTRL[GRS] is
cleared, the eTSEC scans the input data stream for the start of a new frame (preamble sequence and start
of frame delimiter), it resumes receiving, and the first valid frame received is placed in the next available
RxBD.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor 15-147