Tbi Control Register (Tbicon) - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers

15.5.4.3.10 TBI Control Register (TBICON)

Figure 15-128 describes the definition for the TBICON register.
Offset 0x11
0 1
R
Disable
Soft_Reset —
Rx Dis
W
Reset 0 0
Table 15-136 describes the fields of the TBICON register.
Bits Name
0 Soft_Reset Soft reset. This bit is cleared by default.
0 Normal operation.
1 Resets the functional modules in the TBI.
1 — Reserved. (Ignore on read)
2 Disable Rx Dis Disable receive disparity. This bit is cleared by default.
0 Normal operation.
1 Disables the running disparity calculation and checking in the receive direction.
3 Disable Tx Dis Disable transmit disparity. This bit is cleared by default.
0 Normal operation.
1 Disables the running disparity calculation and checking in the transmit direction.
4–6 — Reserved
7 AN Sense Auto-negotiation sense enable. This bit is cleared by default.
0 IEEE 802.3z Clause 37 behavior is desired, which results in the link not completing.
1 Allow the auto-negotiation function to sense either a Gigabit MAC in auto-negotiation bypass mode
8–9 — Reserved
10 Clock Select Clock select. This bit selects how the on-chip TBI PHY is clocked.
This bit is cleared by default.
0 The TBI PHY is clocked by dual split-phase 62.5 MHz receive clocks. These external signals must
1 The TBI PHY is clocked by a single 125 MHz receive clock (required for SGMII operation). This
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-134
2 3 4
Disable
—
Tx Dis
0 0 0 0
Figure 15-128. TBI Control Register Definition
Table 15-136. TBICON Field Descriptions
or an older Gigabit MAC without auto-negotiation capability. If sensed, auto-negotiation complete
becomes true; however, the page received is low, indicating no page was exchanged. Management
can then act accordingly.
be provided via TBI receive clock 0 (TSEC n _RX_CLK) and TBI receive clock 1 (TSEC n _TX_CLK).
If operating in SGMII mode, clearing this bit effectively disables the TBI PHY clock.
single clock, if operating in a non-SGMII (parallel) mode, must be provided via the TBI receive clock
0 (TSEC n _RX_CLK) external signal. If operating in SGMII mode, this clock is provided on-chip by
the SerDes block.
6 7 8 9
AN
—
Sense
0 0 0 0
Description
10 11 12 13
MII
Clock
Mode
Select
0 1 0 0
Freescale Semiconductor
Access: Mixed
14 15
—
0 0