Freescale Semiconductor MPC8313E Family Reference Manual page 265

Offset
0x20 Timer 3 global timers mode register (GTMDR3)
0x22 Timer 4 global timers mode register (GTMDR4)
0x24 Timer 3 global timers reference register (GTRFR3)
0x26 Timer 4 global timers reference register (GTRFR4)
0x28 Timer 3 global timers capture register (GTCPR3)
0x2A Timer 4 global timers capture register (GTCPR4)
0x2C Timer 3 global timers counter register (GTCNR3)
0x2E Timer 4 global timers counter register (GTCNR4)
0x30 Timer 1 global timers event register (GTEVR1)
0x32 Timer 2 global timers event register (GTEVR2)
0x34 Timer 3 global timers event register (GTEVR3)
0x36 Timer 4 global timers event register (GTEVR4)
0x38 Timer 1 global timers prescale register (GTPSR1)
0x3A Timer 2 global timers prescale register (GTPSR2)
0x3C Timer 3 global timers prescale register (GTPSR3)
0x3E Timer 4 global timers prescale register (GTPSR4)
General Purpose (Global) Timer Module 2:
All registers defined for GTM1 are also defined for GTM2; the base address of GTM2 registers is 0x0_06 nn .
5.7.5.1 Global Timers Configuration Registers (GTCFR n )
The global timers configuration registers (GTCFR1 and GTCFR2), shown in
contain configuration parameters used by the timers. These registers allow simultaneous starting, stopping
and resetting of a pair of timers (1 and 2 or 3 and 4) or of a groups of timers (1, 2, 3, and 4) if one bus cycle
is used. GTCFR is cleared by reset.
For proper operation of the timers, do not change the modes of operation and
enable the timer in the same register write operation. The modes can be
changed when GTCFRn[RSTn] is cleared. However, when GTCFRn[RSTn]
are set, they are the only bits that can be changed.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 5-55. GTM Register Address Map (continued)
Register
NOTE
System Configuration
Reset Section/
Access
Value Page
R/W 0x0000 5.7.5.2/5-58
R/W 0xFFFF 5.7.5.3/5-60
R 0x0000 5.7.5.4/5-60
R/W 0x0000 5.7.5.5/5-60
w1c 0x0000 5.7.5.6/5-61
R/W 0x0003 5.7.5.7/5-62
Figure 5-40 and Figure 5-41,
5-55