4.3.2.1
Reset Configuration Word Low Register (RCWLR)
RCWLR is shown in
Figure
word low loaded during the reset flow.
0
1
Field LBCM
DDRCM
16
Field
Table 4-8
defines the RCWLR bit fields.
Bits
Name
0
LBCM
Local bus memory controller clock mode. Selects the local bus controller clock ratio. The local bus
memory controller operates with a frequency equal to the frequency of csb_clk . This bit should be cleared.
1
DDRCM
DDR SDRAM memory controller clock mode. Selects the DDR SDRAM memory controller clock ratio.
The DDR SDRAM memory controller operates at twice the frequency of the csb_clk .
0 csb_clk ratio is 1:1
1 csb_clk ratio is 2:1
2–3
—
Reserved. Must be configured as 2'b10.
4–7
SPMF
System PLL multiplication factor.
8
—
Reserved, should be cleared.
9–15
COREPLL Core PLL configuration. COREPLL sets the ratio between the e300 core clock and the internal csb_clk of
the device. The encodings for COREPLL are given in the hardware specifications for this device.
16–31
—
Reserved, should be cleared.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
4-3. This read-only register gets its values according to the reset configuration
2
3
4
—
SPMF
Figure 4-3. Reset Configuration Word Low Register (RCWLR)
Table 4-8. RCWLR Bit Settings
7
8
9
—
—
Description
Reset, Clocking, and Initialization
COREPLL
15
31
4-13