Freescale Semiconductor MPC8313E Family Reference Manual page 934

Enhanced Three-Speed Ethernet Controllers
Table 15-172. RMII Mode Register Initialization Steps (continued)
(Uses the PHY address (2) and Register address (2) placed in MIIMADD register),
other information about the link is also returned (Extend Status, No pre, Remote Fault, An Ability, Link status, extend Ability)
(Uses the PHY address (2) and Register address (6) placed in MIIMADD register),
read the MII Mgmt AN Expansion register and check bits 13 and 14 (NP Able and Page Rx'd)
MII Mgmt AN Expansion ---> [0000_0000_0000_0000_0000_0000_0000_0110]
Perform an MII Mgmt read cycle of AN Link Partner Base Page Ability Register (Optional)
(Uses the PHY address (2) and Register address (5) placed in MIIMADD register),
read the MII Mgmt AN Link Partner Base Page Ability register and check bits 9 and 10 (Half and Full Duplex)
MII Mgmt AN Link Partner Base Page Ability ---> [0000_0000_0000_0000_0000_00X_1110_0000]
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-204
Perform an MII Mgmt read cycle of Status Register
Set MIIMCOM[Read Cycle]
read the MIIMSTAT register and check bit 10 (AN Done)
MIIMSTAT ---> [0000_0000_0000_0000_0000_0000_0010_0000]
Perform an MII Mgmt read cycle of AN Expansion Register
MIIMADD[0000_0000_0000_0000_0000_0010_0000_0110]
Set MIIMCOM[Read Cycle]
MIIMADD[0000_0000_0000_0000_0000_0010_0000_0101]
Set MIIMCOM[Read Cycle]
Clear IEVENT register,
IEVENT[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize IMASK (Optional)
IMASK[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize GADDR n (Optional)
GADDR n [0000_0000_0000_0000_0000_0000_0000_0000]
Initialize RCTRL (Optional)
RCTRL[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize DMACTRL (Optional)
DMACTRL[0000_0000_0000_0000_0000_0000_0000_0000]
Initialize (Empty) Transmit Descriptor ring and fill buffers with Data
Initialize TBASE0–TBASE7,
TBASE0–TBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Initialize (Empty) Receive Descriptor ring and fill with empty buffers
Initialize RBASE0–RBASE7,
RBASE0–RBASE7[LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_LLLL_L000]
Enable Transmit Queues
Initialize TQUEUE
Enable Receive Queues
Initialize RQUEUE
Enable Rx and Tx,
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0101]
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