Host Controller Capability Parameters (Hccparams); Device Controller Interface Version (Dciversion)—Non-Ehci - Freescale Semiconductor MPC8313E Family Reference Manual

Universal Serial Bus Interface
16.3.1.4

Host Controller Capability Parameters (HCCPARAMS)

HCCPARAMS identifies multiple mode control (time-base bit functionality) addressing capability.
Figure 16-5 shows the HCCPARAMS register.
Offset 0x108
31
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 16-5. Host Control Capability Parameters (HCCPARAMS)
Table 16-7 provides bit descriptions for the HCCPARAMS register.
Bits Name
31–16 — Reserved, should be cleared.
15–8 EECP EHCI extended capabilities pointer. Indicates the existence of a capabilities list. A value of 0x00 indicates
no extended capabilities are implemented. A non-zero value in this register indicates the offset in PCI
configuration space of the first EHCI extended capability. The pointer value must be 0x40 or greater if
implemented to maintain the consistency of the PCI header defined for this class of device.
This field is always 0.
7–4 IST Isochronous scheduling threshold. Indicates, relative to the current position of the executing host controller,
where software can reliably update the isochronous schedule. When bit 7 is zero, the value of the least
significant 3 bits indicates the number of microframes a host controller can hold a set of isochronous data
structures (one or more) before flushing the state. When bit 7 is a one, then host software assumes the host
controller may cache an isochronous data structure for an entire frame.
This field is always 0.
3 — Reserved, should be cleared.
2 ASP Asynchronous schedule park capability. Indicates whether the USB DR module supports the park feature
for high-speed queue heads in the asynchronous schedule. The feature can be disabled or enabled and
set to a specific level by using the asynchronous schedule park mode enable and asynchronous schedule
park mode count fields in the USBCMD register.
This field is always 1 (park feature supported).
1 PFL Programmable frame list flag. Indicates whether system software can specify and use a frame list length
less that 1024 elements. Frame list size is configured via the USBCMD register frame list size field. The
frame list must always be aligned on a 4-K page boundary. This requirement ensures that the frame list is
always physically contiguous.
This field is always 1.
0 ADC 64-bit addressing capability. Always 0; 64-bit addressing is not supported.
0 Data structures use 32-bit address memory pointers
16.3.1.5 Device Controller Interface Version (DCIVERSION)—Non-EHCI
This register is not defined in the EHCI specification. DCIVERSION is a two-byte register containing a
BCD encoding of the device controller interface. The most-significant byte of the register represents a
major revision and the least-significant byte is the minor revision.
register.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
16-10
—
Table 16-7. HCCPARAMS Register Field Descriptions
16 15
EECP
0 0 0 0 0 0 0 0 0 0 0 0
Description
Figure 16-6
Access: Read-only
8 7 4 3 2
IST ASP PFL ADC
—
0 0 1
shows the DCIVERSION
Freescale Semiconductor
1 0
1 0