Freescale Semiconductor MPC8313E Family Reference Manual page 584

DMA/Messaging Unit
12.3.8.6 DMA Byte Count Register (DMABCR n )
DMABCRn contains the number of bytes per transfer (maximum transfer size is 64 Mbytes).
shows the DMABCRn.
Offset 0x120, 0x1A0, 0x220, 0x2A0
31
R
—
W
Reset
Table 12-15 describes the DMABCRn register.
Bits Name
31–26 — Reserved
25–0 BC Byte count. This field contains the number of bytes to transfer. The value in this register is decremented after
each DMA read operation. Maximum transfer size is 64 Mbytes.
12.3.8.7 DMA Next Descriptor Address Register (DMANDAR n )
DMANDARn contains the address for the next segment descriptor in the chain. In chaining mode, this
register is loaded from the 'next descriptor' field of the descriptor to which the current descriptor address
register is pointing. Figure 12-16
Offset 0x124, 0x1A4, 0x224, 0x2A4
31
R
W
Reset
Figure 12-16. DMA Next Descriptor Address Register (DMANDAR n )
Table 12-16 describes the DMANDARn register.
Bits Name
31–5 NDA Next descriptor address. This field contains the next descriptor address of the next segment descriptor in
memory. It must be aligned on an 8-word boundary.
4 NSNEN Next snoop enable.
0 Snooping is disabled on DMA transactions.
1 Snooping is enabled on DMA transactions.
3 NEOSIE Next end-of-segment interrupt enable.
0 No end-of-segment interrupt is generated.
1 An interrupt is generated when the DMA transfer for the next descriptor is finished.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
12-14
26 25
Figure 12-15. DMA Byte Count Register (DMABCR n )
Table 12-15. DMABCR n Field Descriptions
shows the DMANDARn.
NDA
Table 12-16. DMANDAR n Field Descriptions
BC
All zeros
Description
All zeros
Descriptions
Figure 12-15
Access: Read/Write
Access: Read/Write
5 4 3 2 1
NSNEN NESIE — EOTD
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