Ddr Sdram Address Multiplexing - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor
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Table 9-25. Supported DDR1 SDRAM Device Configurations (continued)
SDRAM Device
Device Configuration
1 Gbits
2 Gbits
2 Gbits
1
This configuration is not supported in 16-bit bus mode.
SDRAM Device
Device Configuration
256 Mbits
256 Mbits
512 Mbits
512 Mbits
1 Gbits
1 Gbits
2 Gbits
2 Gbits
4 Gbits
4 Gbits
If a transaction request is issued to the DDR memory controller and the address does not lie within any of
the programmed address ranges for an enabled chip select, a memory select error is flagged.
Using a memory-polling algorithm at power-on reset or by querying the JEDEC serial presence detect
capability of memory modules, system firmware uses the memory-boundary registers to configure the
DDR memory controller to map the size of each bank in memory. The memory controller uses its bank
map to assert the appropriate MCSn signal for memory accesses according to the provided bank starting
and ending addresses. The memory banks are not required to be mapped to a contiguous address space.
9.5.2

DDR SDRAM Address Multiplexing

,
Table
9-27,
Table
9-28,
configuration. The address presented at the memory controller signals MA[14:0] use MA[14] as the msb
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Row × Column ×
Sub-bank Bits
64 Mbits × 16
256 Mbits × 8
128 Mbits × 16
Table 9-26. Supported DDR2 SDRAM Device Configurations
Row × Column ×
Sub-bank Bits
32 Mbits × 8
16 Mbits × 16
64 Mbits × 8
32 Mbits × 16
128 Mbits × 8
64 Mbits × 16
256Mbits × 8
128Mbits × 16
512 Mbits × 8
256 Mbits × 16
Table
9-29,
Table 9-30
32-Bit Bank Size
14 × 10 × 2
256 Mbytes
15 × 11 × 2
1 Gbyte
15 × 10 × 2
512 Mbytes
32-Bit Bank Size
13 × 10 × 2
128 Mbytes
13 × 9 × 2
64 Mbytes
14 × 10 × 2
256 Mbytes
13 × 10 × 2
128 Mbytes
14 × 10 × 3
512 Mbytes
13 × 10 × 3
256 Mbytes
15 × 10 × 3
1 Gbyte
14 × 10 × 3
512 Mbytes
15 × 11 × 3
2 Gbytes
15 × 10 × 3
1 Gbyte
show the address bit encodings for each DDR SDRAM
DDR Memory Controller
Two Banks of Memory
512 Mbytes
2 Gbytes
1 Gbyte
Two Banks of Memory
256 Mbytes
128 Mbytes
512 Mbytes
256 Mbytes
1 Gbyte
512 Mbytes
2 Gbytes
1 Gbyte
4 Gbytes
2 Gbytes
9-35

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