Header Type Configuration Register; Bist Control Configuration Register; Pimmr Base Address Configuration Register - Freescale Semiconductor MPC8313E Family Reference Manual

13.3.3.11 Header Type Configuration Register

Figure 13-29 shows the read-only header type register, which is hard-wired to 0x00.
Offset 0E
7
R
W
Reset

13.3.3.12 BIST Control Configuration Register

Figure 13-30 shows the read-only BIST control register, which is hard-wired to 0x00.
Offset 0x0F
7
R
W
Reset

13.3.3.13 PIMMR Base Address Configuration Register

Figure 13-31 shows the PIMMR base address register fields.
Offset 10
31
R
BA
W
Reset
Table 13-33 shows the bit settings of the PIMMR base address register.
Table 13-33. PIMMR Base Address Configuration Register Field Descriptions
Bits Name
31–20 BA
19–4 —
3 PRE
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Figure 13-29. Header Type Configuration Register
Figure 13-30. BIST Control Configuration Register
20 19
Figure 13-31. PIMMR Base Address Configuration Register
Base address. Defines the base address for the internal (on-chip) memory-mapped register space.
The size of this space is 1 Mbytes.
Reserved
Prefetchable. Hard-wired to 0.
Header Type
3
BIST
All zeros
—
All zeros
Description
PCI Bus Interface
Access: Read-only
Access: Read-only
2
Access: Read/Write
4 3 2
PRE T
0
0
1 0
MSI
13-33