Line Control Registers (Ulcr1 And Ulcr) - Freescale Semiconductor MPC8313E Family Reference Manual

DUART
Table 18-13 describes UAFR fields.
Bits Name
0–5 — Reserved
6 BO Baud clock select
0 The baud clock is not gated off.
1 The baud clock is gated off.
7 CW Concurrent write enable
0 Disables writing to both UART1 and UART2.
1 Enables concurrent writes to corresponding UART registers. A write to a register in UART1 is also a write
to the corresponding register in UART2 and vice versa.
18.3.1.8 Line Control Registers (ULCR1 and ULCR2)
The ULCRs specify the data format for the UART bus and set the divisor latch access bit ULCR[DLAB],
which controls the ability to access the divisor latch least and most significant bit registers and the alternate
function register.
After initializing ULCR, the software should not rewrite the ULCR while valid transfers on the UART bus
are active. The software should not rewrite the ULCR until the last STOP bit is received and no new
characters are being transferred on the bus.
The stick parity bit, ULCR[SP], assigns a set parity value for the parity bit time slot sent on the UART bus.
The set value is defined as mark parity (logic 1) or space parity (logic 0). ULCR[PEN] and ULCR[EPS]
help determine the set parity value. See
be sent at the end of the data transfer. The receiver checks only the first STOP bit, regardless of the number
of STOP bits selected. The word length select bits (1 and 0) define the number of data bits transmitted or
received as a serial character. The word length does not include START, parity, and STOP bits.
Figure 18-10 shows the bits in the ULCRs.
Offset: 0x0_4503, 0x0_4603
0
R
DLAB
W
Reset
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
18-12
Table 18-13. UAFR Field Descriptions
Table 18-15. ULCR[NSTB] defines the number of STOP bits to
1 2
SB SP
Figure 18-10. Line Control Register (ULCR1 and ULCR2)
Description
3 4
EPS PEN
All zeros
Access: Read/write
5 6
NSTB WLS
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