Freescale Semiconductor MPC8313E Family Reference Manual page 299

Note that the PCIPMR1[Power_State] register field maintains its "D3Hot" coding until the device
transitions to D0. This is according to PCI specification. Once the device is awake the e300 will
write the D0 state to the PMCCR1[CURR_STATE]) field, which will then be reflected into the
PCIPMR1[Power_State] field. This indicates to the host that the device has completed the
transition to D0.
4. The PMCCR1[NEXT_STATE] transition triggers the PMC to power up the device. PMC toggles
the external EXT_PWR_CTRL signal to apply voltage to the VDD supply rail. The PMC also
asserts an interrupt to the IPIC. this interrupt as well as the source of the wake-up event will be
stored in PMC registers until cleared by the e300.
5. The PMC then waits for the PMC_PWR_OK signal to be asserted. PMC_PWR_OK is an
indication that the external VDD supply is stable and within spec. The PMC_PWR_OK signal is
an input to the PMC that can be supplied from an external source, or can be tied active internally.
The source is determined by GPIO mux logic. If the system is designed to supply PMC_PWR_OK
externally the mux logic would be programmed to bring PMC_PWR_OK in on the IIC2_SDA
input. If the system does not supply this signal mux logic would be programmed to supply the
IIC2_SDA signal on this input and PMC_PWR_OK would be forced active internally.
6. When the PMC_PWR_OK signal asserts, the PMC's reset timer begins to count down. If the
PMC_PWR_OK signal is programmed to be asserted externally but never asserts, this is a failure
condition. The host must detect this failure through time-out by polling the agent's state, which will
never change.
7. The PMC asserts a reset to the logic blocks in the powered-off region upon entering the low power
mode (D3Warm). This reset signal is ORed with the hard reset asserted during chip POR. When a
wake-up event occurs the reset signal continues to be asserted for the duration of the reset timer
count. This is to allow the e300 PLL to lock. During wake-up the reset configuration word (RCW)
is not reloaded. The e300 PLL locks with previous RCW settings. The length of the PMC reset is
programmable via software and must be initialized by an e300 device driver before power down.
Guidelines will be provided as to the required length of this PMC reset.
Note that if the PMC_PWR_OK signal is not used, permanently asserted, the value of the reset time
should be increased to account for VDD becoming stable.
8. When the PMC reset timer expires, the pmc_reset is de-asserted and the conditioning logic is
removed allowing the powered on and powered off regions of the die to operate normally.
9. The e300 begins fetching instructions just as it did when initially reset (POR), starting at the
memory address specified by MSRP[IP]. This address is decoded by the local address window
logic (eLBC) and directed to a particular boot device.
10. The e300's initialization code checks the PMCCR1[POWER_OFF] bit to see that this is a reset
from the D3Warm state, not a full POR. The e300 initializes the DDR controller so that it does not
do an initialization of the DDR when coming out of self-refresh (DDR_SDRAM_CFG[BI] = 1).
11. The initialization code initializes the IPIC controller and the MSR[EE] such that the e300 can see
pending interrupts including those from the PMC. After responding, the e300 clears the IPIC,
PMC, and eTSEC interrupts.
12. The PMCCR1[CURR_STATE] register field is updated to reflect the new active state. This update
is reflected in the PCIPMR1[Power_State] field indicating to the PCI host that the device has
returned to its active state.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
System Configuration
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