Dma Memory Map/Register Definition - Freescale Semiconductor MPC8313E Family Reference Manual

DMA/Messaging Unit
— Data chaining and direct mode
— Interrupt on completed segment, chain, and error
12.2

DMA Memory Map/Register Definition

Table 12-1 lists the address and access of the memory map module.
Offset
0x0_8030 OMISR—Outbound message interrupt status register
0x0_8034 OMIMR—Outbound message interrupt mask register
0x0_8050 IMR0—Inbound message register 0
0x0_8054 IMR1—Inbound message register 1
0x0_8058 OMR0—Outbound message register 0
0x0_805C OMR1—Outbound message register 1
0x0_8060 ODR—Outbound doorbell register
0x0_8068 IDR—Inbound doorbell register
0x0_8080 IMISR—Inbound message interrupt status register
0x0_8084 IMIMR—Inbound message interrupt mask register
0x0_8100 DMAMR0—DMA 0 mode register
0x0_8104 DMASR0—DMA 0 status register
0x0_8108 DMACDAR0—DMA 0 current descriptor address register
0x0_8110 DMASAR0—DMA 0 source address register
0x0_8118 DMADAR0—DMA 0 destination address register
0x0_8120 DMABCR0—DMA 0 byte count register
0x0_8124 DMANDAR0—DMA 0 next descriptor address register
0x0_8180 DMAMR1—DMA 1 mode register
0x0_8184 DMASR1—DMA 1 status register
0x0_8188 DMACDAR1—DMA 1 current descriptor address register
0x0_8190 DMASAR1—DMA 1 source address register
0x0_8198 DMADAR1—DMA 1 destination address register
0x0_81A0 DMABCR1—DMA 1 byte count register
0x0_81A4 DMANDAR1—DMA 1 next descriptor address register
0x0_8200 DMAMR2—DMA 2 mode register
0x0_8204 DMASR2—DMA 2 status register
0x0_8208 DMACDAR2—DMA 2 current descriptor address register
0x0_8210 DMASAR2—DMA 2 source address register
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
12-2
Table 12-1. Module Memory Map
Register Access Reset
Mixed All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
Mixed All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
R/W All zeros
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Section/Page
12.3.1/12-3
12.3.2/12-4
12.3.3/12-5
12.3.3/12-5
12.3.4/12-5
12.3.4/12-5
12.3.5/12-6
12.3.5/12-6
12.3.6/12-7
12.3.7/12-8
12.3.8.1/12-9
12.3.8.2/12-11
12.3.8.3/12-12
12.3.8.4/12-13
12.3.8.5/12-13
12.3.8.6/12-14
12.3.8.7/12-14
12.3.8.1/12-9
12.3.8.2/12-11
12.3.8.3/12-12
12.3.8.4/12-13
12.3.8.5/12-13
12.3.8.6/12-14
12.3.8.7/12-14
12.3.8.1/12-9
12.3.8.2/12-11
12.3.8.3/12-12
12.3.8.4/12-13