Device Operational Model; Device Controller Initialization - Freescale Semiconductor MPC8313E Family Reference Manual

Bits
31–12 Buffer Pointer. Selects the page offset in memory for the packet buffer. Non virtual memory systems will typically set
the buffer pointers to a series of incrementing integers.
11 Reserved
10–0 Frame Number. Written by the device controller to indicate the frame number in which a packet finishes. This is
typically be used to correlate relative completion times of packets on an ISO endpoint.
Bits
31–12 Buffer Pointer. Selects the page offset in memory for the packet buffer. Non virtual memory systems will typically set
the buffer pointers to a series of incrementing integers.
11–0 Reserved
16.8

Device Operational Model

The function of the device operation is to transfer a request in the memory image to and from the Universal
Serial Bus. Using a set of linked list transfer descriptors, pointed to by a queue head, the device controller
will perform the data transfers. The following sections explain the use of the device controller from the
device controller driver (DCD) point-of-view and further describe how specific USB bus events relate to
status changes in the device controller programmer's interface.
16.8.1

Device Controller Initialization

After hardware reset, the USB DR module is disabled until the run/stop bit (USBCMD[RS]) is set to a '1'.
In the disabled state, the pull-up on the USB D+ is not active which prevents an attach event from
occurring. At a minimum, it is necessary to have the queue heads setup for endpoint zero before the device
attach occurs. Shortly after the device is enabled, a USB reset will occur followed by setup packet arriving
at endpoint 0. A queue head must be prepared so that the device controller can store the incoming setup
packet.
The MPC8313E USB PHY and clock must be configured prior to initialization of the USB controller.
Initialization of the MPC8313E USB PHY interface is performed via software control following a
power-on reset.
The device can be configured for either the internal UTMI PHY or an external ULPI PHY enabled with
various clocking options. The configuration of each PHY interface and the various clocking options are
detailed below.
To configure the internal UTMI PHY the following initialization sequence is required:
1. After power-on reset the UTMI PHY will be in disabled state and the PLL will be held reset.
2. Set the CONTROL[REFSEL] bits, 24–25 to correspond to the UTMI PLL the appropriate
reference clock frequency.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Table 16-81. Buffer Pointer Page 1
Description
Table 16-82. Buffer Pointer Pages 2–4
Description
Universal Serial Bus Interface
16-131