Interfacing To Peripherals In Different Address Modes; Multiplexed Address/Data Bus For 26-Bit Addressing; Non-Multiplexed Address And Data Buses - Freescale Semiconductor MPC8313E Family Reference Manual

10.5 Initialization/Application Information
This section provides information about the following:
• Section 10.5.1, "Interfacing to Peripherals in Different Address Modes"
• Section 10.5.2, "Bus Turnaround"
• Section 10.5.3, "Interface to Different Port-Size Devices"
• Section 10.5.4, "Command Sequence Examples for NAND Flash EEPROM"
• Section 10.5.5, "Interfacing to Fast-Page Mode DRAM Using UPM"
• Section 10.5.6, "Interfacing to ZBT SRAM Using UPM"
10.5.1

Interfacing to Peripherals in Different Address Modes

This section provides guidelines for interfacing to peripherals.
10.5.1.1

Multiplexed Address/Data Bus for 26-Bit Addressing

In this mode, the eLBC is used with port sizes of 8 and 16 bits; address bits A[6:21] will appear on
LAD[0:15] (with zero bits on LAD[16:31]) during address phases, while the lower 10 bits of the address,
A[22:31], are driven permanently on LA[16:25]. The connection is illustrated in
Local Bus Interface
LAD[0:15]
LA[16:25]
Figure 10-69. Multiplexed Address/Data Bus for 26-Bit Addressing
10.5.1.2

Non-Multiplexed Address and Data Buses

For small address space applications the address latch may be eliminated entirely if the local bus address
is taken entirely from LA[0:25], in which case addresses driven onto LAD during address phases are
simply ignored. The connection is illustrated in
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
D
LAD[0:15]
LE
LALE
Muxed Address/Data
Unmuxed Address
Q
Latch
Figure 10-70. In non-multiplexed mode, the waveforms
Enhanced Local Bus Controller
Figure 10-69.
Device
D[15:0]
A[21:6]
A[31:22]
10-91