Clock Interface Signals - Freescale Semiconductor MPC8313E Family Reference Manual

Table 9-3. Memory Interface Signals—Detailed Signal Descriptions (continued)
Signal I/O
MCS[0:1] O Chip selects. Two chip selects supported by the memory controller.
Meaning
Timing Assertion/Negation—Asserted to signal any new transaction to the SDRAM. The transaction
MWE O Write enable. Asserted when a write transaction is issued to the SDRAM. This is also used for mode
registers set commands and precharge commands.
Meaning
Timing Assertion/Negation—Similar timing as MRAS and MCAS. Used for write commands.
MDM[0:3] O DDR SDRAM data output mask. Masks unwanted bytes of data transferred during a write. They are
needed to support sub-burst-size transactions (such as single-byte writes) on SDRAM where all I/O
occurs in multi-byte bursts. MDM0 corresponds to the most significant byte (MSB).
byte lane encodings.
Meaning
Timing Assertion/Negation—Same timing as MDQx as outputs.
MODT[0:1] O On-Die termination. Memory controller outputs for the ODT to the DRAM. MODT[0:1] represents the
Meaning
Timing Assertion/Negation—Driven in accordance with JEDEC DRAM specifications for on-die
9.3.2.2

Clock Interface Signals

Table 9-4 contains the detailed descriptions of the clock signals of the DDR controller.
Signal I/O
MCK, O DRAM clock output and its complement. See
MCK
State
Meaning
Timing Assertion/Negation—Timing is controlled by the DDR_CLK_CNTL register at offset 0x130.
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State Asserted—Selects a physical SDRAM bank to perform a memory operation as described in
Section 9.4.1.1, "Chip Select Memory Bounds (CSn_BNDS),"
"Chip Select Configuration (CSn_CONFIG)."
MCS[0:1] signals to begin a memory cycle.
Negated—Indicates no SDRAM action during the current cycle.
must adhere to the timing constraints set in TIMING_CFG_0–TIMING_CFG_3.
High impedance—Always driven unless the memory controller is disabled.
State Asserted—Indicates a memory write operation. See
states required on MWE for various other SDRAM commands.
Negated—Indicates a memory read operation.
High impedance—MWE is always driven unless the memory controller is disabled.
State Asserted—Prevents writing to DDR SDRAM. Asserted when data is written to DRAM if the
corresponding byte(s) should be masked for the write. Note that the MDM n signals are
active-high for the DDR controller. MDM n is part of the DDR command encoding.
Negated—Allows the corresponding byte to be read from or written to the SDRAM.
High-impedance—Always driven unless the memory controller is disabled.
on-die termination for the associated data, data masks, and data strobes.
State Asserted/Negated—Represents the ODT driven by the DDR memory controller.
termination timings. It is configured through the CS n _CONFIG[ODT_RD_CFG] and
CS n _CONFIG[ODT_WR_CFG] fields.
High impedance—Always driven.
Table 9-4. Clock Signals—Detailed Signal Descriptions
Asserted/Negated—The JEDEC DDR SDRAM specifications require true and complement
clocks. A clock edge is seen by the SDRAM when the true and complement cross.
Description
The DDR controller asserts one of the
Table 9-32
Description
Section 9.5.4.1, "Clock Distribution."
DDR Memory Controller
and Section 9.4.1.2,
for more information on the
Table 9-24 shows
9-7