Freescale Semiconductor MPC8313E Family Reference Manual page 126

Memory Map
Offset
0x2_4114 TQUEUE—Transmit queue control register
0x2_4118– Reserved
0x2_413C
0x2_4140 TR03WT—TxBD rings 0–3 round-robin weightings
0x2_4144 TR47WT—TxBD rings 4–7 round-robin weightings
0x2_4148– Reserved
0x2_417C
0x2_4180 TBDBPH–Tx data buffer pointer high bits
0x2_4184 TBPTR0—TxBD pointer register for ring 0
0x2_4188 Reserved, should be cleared
0x2_418C TBPTR1—TxBD pointer register for ring 1
0x2_4190 Reserved
0x2_4194 TBPTR2—TxBD pointer register for ring 2
0x2_4198 Reserved
0x2_419C TBPTR3—TxBD pointer register for ring 3
0x2_41A0 Reserved
0x2_41A4 TBPTR4—TxBD pointer register for ring 4
0x2_41A8 Reserved
0x2_41AC TBPTR5—TxBD pointer register for ring 5
0x2_41B0 Reserved
0x2_41B4 TBPTR6—TxBD pointer register for ring 6
0x2_41B8 Reserved
0x2_41BC TBPTR7—TxBD pointer register for ring 7
0x2_41C0– Reserved
0x2_41FC
0x2_4204 TBASE0—TxBD base address of ring 0
0x2_4208 Reserved, should be cleared
0x2_420C TBASE1—TxBD base address of ring 1
0x2_4210 Reserved
0x2_4214 TBASE2—TxBD base address of ring 2
0x2_4218 Reserved
0x2_421C TBASE3—TxBD base address of ring 3
0x2_4220 Reserved
0x2_4224 TBASE4—TxBD base address of ring 4
0x2_4228 Reserved
0x2_422C TBASE5—TxBD base address of ring 5
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
2-20
Table 2-2. Memory Map (continued)
Register Access Reset
R/W 0x0000_8000
— —
R/W 0x0000_0000
R/W 0x0000_0000
— —
R/W 0x0000_0000
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
— —
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
— —
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
Freescale Semiconductor
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