Gigabit Ethernet Frame Transmission - Freescale Semiconductor MPC8313E Family Reference Manual

5. Load TBASE0–TBASE7 with new Tx BD pointers
6. Load RBASE0–RBASE7 with new Rx BD pointers
7. Setup other MAC registers (MACCFG2, MAXFRM, and so on)
8. Setup group address hash table (GADDR0–GADDR15) if address filtering is required
9. Setup receive frame filer table (through RQFAR, RQFCR, and RQFPR) if filing to multiple RxBD
rings is required
10. Setup WWR, WOP, TOD bits in DMACTRL register
11. Enable transmit queues in TQUEUE, and ensure that the transmit scheduling mode is correctly set
in TCTRL.
12. Enable receive queues in RQUEUE, and optionally set TOE functionality in RCTRL.
13. Clear THLT and TXF bits in TSTAT register by writing 1 to them
14. Clear QHLT and RXF bits in RSTAT register by writing 1 to them.
15. Clear GRS/GTS bits in DMACTRL (do not change other bits)
16. Enable Tx_EN/Rx_EN in MACCFG1 register
15.6.2.3

Gigabit Ethernet Frame Transmission

The Ethernet transmitter requires little core intervention. After the software driver initializes the system,
the eTSEC begins to poll the first transmit buffer descriptor (TxBD) in TxBD ring 0 every 512 transmit
clocks. If TxBD[R] is set, and the TxBD ring is scheduled for transmission, the eTSEC begins copying the
associated transmit buffer from memory to its Tx FIFO. The transmitter takes data from the Tx FIFO and
transmits data to the MAC. The MAC transmits the data through the GMII interface to the physical media.
The transmitter, once initialized, runs until the end-of-frame (EOF) condition is detected unless a collision
within the collision window occurs (half-duplex mode) or an abort condition is encountered.
If the user has a frame ready to transmit, setting the DMACTRL[TOD] eliminates waiting for the next poll
and a DMA transfer of the transmit data buffers can begin immediately. The transmission begins once all
data for the frame is loaded into the Tx FIFO or sufficient transmit data (determined by the Tx FIFO
threshold register) is in the Tx FIFO. If the line is not busy, the MAC transmit logic asserts TX_EN and
sends the 7-octet preamble sequence, 1-octet start of frame delimiter, and frame information in that order.
If the line is busy, the controller waits for the carrier sense signal, CRS, to remain inactive for 60 bit times
(60 clocks) and transmission begins after an additional 36 bit times (96 bit times after CRS became active).
In full-duplex mode, because collisions are ignored, frame transmission maintains only the interframe gap
(96 bit times) regardless of CRS.
In half-duplex mode (MACCFG2[Full Duplex] is cleared) the MAC defers transmission if the line is busy
(CRS asserted). Before transmitting, the MAC waits for carrier sense to become inactive, at which point
it then determines if CRS remains negated for 60 clocks. If so, transmission begins after an additional 36
bit times (96 bit times after CRS originally became negated). If CRS continues to be asserted, the MAC
follows a specified back-off procedure and tries to retransmit the frame until the retry limit is reached. Data
stored in the Tx FIFO is re-transmitted in case of a collision. This avoids unnecessary memory traffic.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Enhanced Three-Speed Ethernet Controllers
15-145