Freescale Semiconductor MPC8313E Family Reference Manual page 734

Enhanced Three-Speed Ethernet Controllers
– In addition to primary station address, up to fifteen additional exact-match MAC addresses
supported
— Broadcast address (accept/reject)
— Hash table match on up to 256 unicast/multicast or 512 multicast-only addresses
— Promiscuous mode
• Remote network monitoring (RMON) statistics support
— 32-bit byte counters
— Carry/Overflow of counter interrupts
• Backward compatibility with MPC8349E (PowerQUICC II Pro) TSEC
— PowerQUICC II Pro buffer descriptor (BD) format and rings supported
— Common register memory map, with specific exceptions:
– Out-of-sequence transmit BD not supported
– Internal DMA BD pointers and data counts not visible
– MINFLR register not supported
— Reset state of eTSEC defaults to common PowerQUICC II Pro TSEC subset
— TSEC_ID register permits TSEC versus enhanced TSEC differentiation
• Hardware assist for 1588-compliant timestamping (1588 not supported in conjunction with SGMII
10/100)
— Per packet timestamp tag for Receive
— Programmable timestamp capture for Transmit
— Recognition of PTP packet
— Periodic Pulse Generation
— Self-correcting precision timer with nano-second resolution
— Phase aligned adjustable (divide by N) clock output
— Two 64-bit alarm (future time) registers for future time comparison
15.3 Modes of Operation
The eTSEC's primary operational modes are the following:
• Full- and half-duplex operation
This is determined by the MACCFG2 register's full-duplex bit (MACCFG2[Full Duplex]).
Full-duplex mode is intended for use on point-to-point links between switches or end node to
switch. Half-duplex mode is used in connections between an end node and a repeater or between
repeaters.
If configured in half-duplex mode (10- and 100-Mbps operation; MACCFG2[Full Duplex] is
cleared), the MAC complies with the IEEE CSMA/CD access method.
If configured in full-duplex mode (10/100/1000 Mbps operation; MACCFG2[Full Duplex] is set),
the MAC supports flow control. If flow control is enabled, it allows the MAC to receive or send
PAUSE frames.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-4 Freescale Semiconductor