Pci Interrupt Acknowledge Register (Pci_Int_Ack); Pci Memory-Mapped Control And Status Registers; Pci Error Status Register (Pci_Esr) - Freescale Semiconductor MPC8313E Family Reference Manual

This register may be accessed with an 8-, 16-, or 32-bit access, depending on the width of the register
targeted by the configuration transaction.
Figure 13-4 shows the PCI_CONFIG_DATA register fields.
Offset 0x4
31
R
W
Reset
Table 13-7 shows the bit settings of the PCI_CONFIG_DATA register.
Bits Name
31–0 CFG_DATA Configuration data. This field contains the data transferred on a PCI configuration transaction.
13.3.1.3

PCI Interrupt Acknowledge Register (PCI_INT_ACK)

Reading this register generates an interrupt acknowledge transaction on the PCI bus. The value that is read
is undefined.
13.3.2

PCI Memory-Mapped Control and Status Registers

This section describes the control and status registers.
13.3.2.1

PCI Error Status Register (PCI_ESR)

The PCI error status register (PCI_ESR) contains status bits for various types of error conditions captured
by the PCI controller. Each status bit is set when the corresponding error condition is captured. PCI_ESR
is a write-1-to-clear type register. A bit is cleared whenever the register is written and the data in the
corresponding bit location is a 1.
Offset 0x00
0 1
R MERR
W w1c
Reset
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Figure 13-4. PCI_CONFIG_DATA
Table 13-7. PCI_CONFIG_DATA Field Descriptions
Figure 13-5 shows the PCI_ESR fields.
20
APAR PCISERR MPERR TPERR NORSP TABT
—
w1c
Figure 13-5. PCI Error Status Register (PCI_ESR)
CFG_DATA
All zeros
Description
21 22 23
w1c w1c
All zeros
PCI Bus Interface
Access: Read/Write
Access: w1c
24 25 26 27
w1c w1c w1c
0
31
—
13-15