Descriptor Buffer (Db) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

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The fetch FIFO can hold up to 24 descriptor pointers at a time. When the end of the current descriptor is

reached, the descriptor pointed to by the next location in the fetch FIFO will be read to launch the next

The Fetch Address is written into the FIFO only if the write includes the least significant byte (bits 56–63).

If Extended Address mode is used, the Extended Fetch Address must be written before or concurrent with

the Fetch Address.

Specifying a FETCH_ADRS of 0 causes the channel to generate an error and stop.

describes the fetch FIFO fields.

Descriptor Buffer (DB)

The descriptor buffer (DB) consists of 8 dword registers (DB0–DB7), and contains the current descriptor

being processed by the channel. These registers are read-only, since the descriptor is always fetched from

system memory.

For more information about the fields in a descriptor, see

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Freescale Semiconductor

Figure 14-39. Fetch FIFO Register (FF)

Table 14-38. Fetch FIFO Field Descriptions

Reserved, set to zero

Fetch address. Pointer to system memory location of a descriptor the host wants the SEC to fetch.

Channel_1 0x3_1180–0x3_11BF

Figure 14-40. Descriptor Buffer (DB)

Channel_1 0x3_01148

Section 14.3.1, "Descriptor Structure."

Security Engine (SEC) 2.2

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