Freescale Semiconductor MPC8313E Family Reference Manual page 594

PCI Bus Interface
PCI Interface
PCI Bus Interface
Regs
PME
PCI
Controller
Arb
HotSwap
I/O Sequencer
Coherency System Bus (CSB)
Figure 13-1. PCI Controller Block Diagram
The PCI controller connects the processor and memory system to the I/O components through the PCI
system bus. This interface acts as both initiator (master) and target (slave) device. The PCI controller uses
a 32-bit multiplexed, address/data bus that can run at frequencies up to 66-MHz. The interface provides
address and data parity with error checking and reporting. The interface provides for three physical address
spaces—64-bit address memory, 32-bit address I/O, and PCI configuration space.
Note that PCI supports up to three external masters.
The PCI interface can function as either a PCI host bridge referred to as host mode or a peripheral device
on the PCI bus referred to as agent mode. See Section 13.4.4.4, "Host Mode Configuration Access," for
more information. Note that the PCI controller can be configured from the PCI bus while in agent mode.
An address translation mechanism is provided to map PCI memory windows between the PCI bus and the
internal bus.
The PCI interface does not flush pending outbound writes as a result of an inbound read command.
Systems must not rely on inbound reads to ensure all pending outbound writes have completed. For
example, consider the case where a core writes data to a PCI device and then updates a flag in the local
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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