Freescale Semiconductor MPC8313E Family Reference Manual page 600

PCI Bus Interface
Table 13-3. PCI Interface Signals—Detailed Signal Descriptions (continued)
Signal I/O
PCI_INTA O
PCI_IRDY I/O PCI initiator ready. This signal is driven by the PCI controller when it is the initiator of a PCI transfer.
O
I
PCI_PAR I/O PCI parity.
O
I
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
13-8
PCI interrupt A.
State Asserted—The PCI controller signals an interrupt to the PCI host.
Meaning Negated—The PCI controller is not currently signalling an interrupt.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Outputs for the bi-directional initiator ready.
State Asserted—The PCI controller, acting as a PCI master, can complete the current data
Meaning phase of a PCI transaction. During a write, this PCI controller asserts PCI_IRDY to
indicate that valid data is present on PCI_AD[31:0]. During a read, this PCI controller
asserts PCI_IRDY to indicate that it is prepared to accept data.
Negated—The PCI target needs to wait before this PCI controller, acting as a PCI master,
can complete the current data phase. During a write, this PCI controller negates
PCI_IRDY to insert a wait cycle when it cannot provide valid data to the target.
During a read, this PCI controller negates PCI_IRDY to insert a wait cycle when it
cannot accept data from the target.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Inputs for the bi-directional initiator ready.
State Asserted—Another PCI master can complete the current data phase of a transaction.
Meaning Negated—If PCI_FRAME is asserted, indicates a wait cycle from another master. If
PCI_FRAME is negated, indicates that the PCI bus is idle.
Outputs for the bi-directional parity.
State Asserted—Odd parity across PCI_AD[31:0] and PCI_CBE[3:0] during address and data
Meaning phases.
Negated—Even parity across PCI_AD[31:0] and PCI_AD[31:0] during address and data
phases.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Inputs for the bi-directional parity.
State Asserted—Odd parity driven by another PCI master or the PCI target during address and
Meaning data phases.
Negated—Even parity driven by another PCI master or the PCI target during address and
data phases.
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.3
Description
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