Interrupt Status Register (Isr) - Freescale Semiconductor MPC8313E Family Reference Manual

Security Engine (SEC) 2.2
Table 14-39 describes the register field names in the interrupt mask register (IMR), interrupt status register
(ISR), and interrupt clear register (ICR).
I
Table 14-39. Field Names in Interrupt Mask, Interrupt Status, and Interrupt Clear Registers
Bits Names
15 ITO
20–23 Done
Overflow
30–31 Err and Dn bits
for channel
Multiple Err and Dn bits
for execution
units (AESU,
and so on.)
0–14, —
16–19,
24–29,
32–53,
56–57,
60–61
14.6.4.3

Interrupt Status Register (ISR)

The interrupt status register (ISR) contains fields representing all possible sources of interrupts. The
interrupt status register is cleared either by a reset, or by writing the appropriate bits active in the interrupt
clear register (ICR). Figure 14-43
are described in Table
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
14-70
Internal time out
0 No internal time out
1 An internal time out was detected
Note: Internal time out is an indication that the channel or EU has failed to respond to a slave read
or write within 16 cycles, which would only occur in an impending hang condition. Assertion
of this interrupt indicates the SEC controller has completed the transaction to avoid a hang,
however the 'completed' transaction does not result in a successful read or write, and the
interrupt advises the system that the slave transaction was unsuccessful.
Done overflow (one bit for each channel)
0 No done overflow
1 Done overflow error. Indicates that more than 15 done interrupts were queued from the channel
without an interrupt clear from the host.
Err
0 No error detected
1 Error detected. Indicates that channel status register must be read to determine exact cause of
the error.
Dn
0 Not DONE
1 DONE bit indicates that the interrupting channel has completed its operation.
Err
0 No error detected.
1 Error detected. Indicates that execution unit status register must be read to determine exact
cause of the error.
Dn
0 Not DONE.
1 DONE bit indicates that the interrupting EU has completed its operation.
Reserved, set to zero.
shows the bit positions of each potential interrupt source. The bit fields
14-39.
Description
Freescale Semiconductor