Freescale Semiconductor MPC8313E Family Reference Manual page 112

Memory Map
Offset
0x0_0200– Reserved, should be cleared
0x0_0203
0x0_0204 SWCRR—System watchdog control register
0x0_0208 SWCNR—System watchdog count register
0x0_020C– Reserved, should be cleared
0x0_020D
0x0_020E SWSRR—System watchdog service register
0x0_0300 RTCNR—Real time counter control register
0x0_0304 RTLDR—Real time counter load register
0x0_0308 RTPSR—Real time counter prescale register
0x0_030C RTCTR—Real time counter register
0x0_0310 RTEVR—Real time counter event register
0x0_0314 RTALR—Real time counter alarm register
0x0_0318– Reserved, should be cleared
0x0_031F
0x0_0400 PTCNR—Periodic interval timer control register
0x0_0404 PTLDR—Periodic interval timer load register
0x0_0408 PTPSR—Periodic interval timer prescale register
0x0_040C PTCTR—Periodic interval timer counter register
0x0_0410 PTEVR—Periodic interval timer event register
0x0_0410– Reserved, should be cleared
0x0_041F
0x0_0500 GTCFR1—Timer 1 and 2 global timers configuration
register
0x0_0501– Reserved, should be cleared
0x0_0503
0x0_0504 GTCFR2—Timer 3 and 4 global timers configuration
register
0x0_0505– Reserved, should be cleared
0x0_050F
0x0_0510 GTMDR1—Timer 1 global timers mode register
0x0_0512 GTMDR2—Timer 2 global timers mode register
0x0_0514 GTRFR1—Timer 1 global timers reference register
0x0_0516 GTRFR2—Timer 2 global timers reference register
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
2-6
Table 2-2. Memory Map (continued)
Register
Watchdog Timer (WDT) Registers
Real Time Clock Module Registers (RTC)
Periodic Interval Timer (PIT) Registers
Global Timers Module 1
Access Reset
— —
R/W 0x0000_0007
R 0x0000_FFFF
— —
R/W 0x0000
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
R/W 0xFFFF_FFFF
— —
R/W 0x0000_0000
R/W 0x0000_0000
R/W 0x0000_0000
R 0x0000_0000
R/W 0x0000_0000
— —
R/W 0x00
— —
R/W 0x00
— —
R/W 0x0000
R/W 0xFFFF
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