Ipic Memory Map/Register Definition - Freescale Semiconductor MPC8313E Family Reference Manual

Integrated Programmable Interrupt Controller (IPIC)
Table 8-2. IPIC External Signals—Detailed Signal Descriptions (continued)
Signal I/O
PCI_INTA OD Interrupt request out. Active-low, open drain. When the IPIC is programmed in core disable mode, this output
reflects the raw interrupts generated by on-chip sources. See
details.
State
Meaning
Timing Because external interrupts are asynchronous with respect to the system clock, both
MCP_OUT OD Non-maskable Interrupt (machine check) request out. Active-low, open drain. When the IPIC is programmed
in core disable mode, this output reflects the mcp interrupts generated by on-chip sources. See
"IPIPC Modes of Operation."
State
Meaning
Timing Because external interrupts are asynchronous with respect to the system clock, both
8.5

IPIC Memory Map/Register Definition

The IPIC programmable register map occupies 256 bytes of memory-mapped space. Reading undefined
portions of the memory map returns all zeros; writing has no effect.
All IPIC registers are 32 bits wide and they are located on 32-bit address boundaries. Software can perform
byte, half-word or word accesses to any IPIC registers. All addresses used in this chapter are offsets from
the IPIC base, as defined in
Table 8-3 shows the memory map of the IPIC unit.
Offset
0x00 System global interrupt configuration register (SICFR)
0x04 System regular interrupt vector register (SIVCR)
0x08 System internal interrupt pending register (SIPNR_H)
0x0C System internal interrupt pending register (SIPNR_L)
0x10 System internal interrupt group A priority register (SIPRR_A)
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
8-6
Asserted—At least one interrupt is currently being signalled to the external system.
Negated—Indicates no interrupt source currently routed to IRQ_OUT.
assertion and negation of IRQ_OUT occur asynchronously with respect to the interrupt source. All
timing given here is approximate.
Assertion—Internal interrupt source: 3 system bus clock cycles after the interrupt occurs. External
interrupt source: 4 cycles after the interrupt occurs.
Negation—Follows interrupt source negation with the following delay:
Internal interrupt: 3 system bus clock cycles. External interrupt: 4 cycles.
Asserted—At least one machine check interrupt is currently being signalled to the external system.
Negated—Indicates no interrupt source currently routed to MCP_OUT.
assertion and negation of MCP_OUT occurs asynchronously with respect to the interrupt source.
All timing given here is approximate.
Assertion—Internal interrupt source: 2 system bus clock cycles after interrupt occurs. External
interrupt source: 4 cycles after interrupt occurs.
Negation—Follows interrupt source negation with the following delay:
Internal interrupt: 2 system bus clock cycles. External interrupt: 4 cycles.
Chapter 2, "Memory Map."
Table 8-3. IPIC Register Address Map
Register
Description
Section 8.3, "IPIPC Modes of Operation,"
Access
R/W
R
R
R
R/W
Section 8.3,
Section/
Reset Value
Page
All zeros 8.5.1/8-7
All zeros 8.5.2/8-9
All zeros 8.5.3/8-11
All zeros 8.5.3/8-11
0x0530_9770 8.5.4/8-13
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