Freescale Semiconductor MPC8313E Family Reference Manual page 9

Paragraph
Number
5.8.2.4 Power Management Controller Configuration Register 1 (PMCCR1).................. 5-71
5.8.2.5 Power Management Controller Configuration Register 2 (PMCCR2).................. 5-73
5.8.3 Functional Description............................................................................................... 5-74
5.8.3.1 Dynamic Power Management................................................................................ 5-74
5.8.3.2 Shutting Down Unused Blocks.............................................................................. 5-75
5.8.3.3 Software-Controlled Power-Down States.............................................................. 5-75
5.8.3.4 Software-Controlled Power Supply Switching...................................................... 5-75
5.8.3.5 Support of PCI Power Management Interface Specification................................. 5-76
5.8.3.5.1
5.8.3.5.2
5.8.3.6 Exiting Core and System Low Power States ......................................................... 5-80
5.8.3.6.1
5.8.3.6.2
5.8.3.7 MPC8313E-Specific PMC Low Power States ...................................................... 5-81
5.8.3.7.1
5.8.3.7.2
5.8.3.7.3
5.8.3.7.4
5.8.4 Initialization/Application Information ....................................................................... 5-93
5.8.4.1 Core Disable in Low Power Mode ........................................................................ 5-93
6.1 Arbiter Overview ............................................................................................................. 6-1
6.1.1 Coherent System Bus Overview .................................................................................. 6-1
6.2 Arbiter Memory Map/Register Definition ....................................................................... 6-2
6.2.1 Arbiter Configuration Register (ACR) ........................................................................ 6-2
6.2.2 Arbiter Timers Register (ATR) .................................................................................... 6-4
6.2.3 Arbiter Event Enable Register (AEER) ....................................................................... 6-5
6.2.4 Arbiter Event Register (AER)...................................................................................... 6-6
6.2.5 Arbiter Interrupt Definition Register (AIDR).............................................................. 6-7
6.2.6 Arbiter Mask Register (AMR)..................................................................................... 6-8
6.2.7 Arbiter Event Attributes Register (AEATR)................................................................ 6-9
6.2.8 Arbiter Event Address Register (AEADR)................................................................ 6-10
6.2.9 Arbiter Event Response Register (AERR)................................................................. 6-11
6.3 Functional Description................................................................................................... 6-12
6.3.1 Arbitration Policy ...................................................................................................... 6-12
6.3.1.1 Address Bus Arbitration with PRIORITY[0:1] ..................................................... 6-12
6.3.1.2 Address Bus Arbitration with REPEAT ................................................................ 6-13
6.3.1.3 Address Bus Arbitration After ARTRY................................................................. 6-14
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
Freescale Semiconductor
Contents
Entering Low Power States-Core-Only Mode ................................................ 5-79
Entering Low Power States-Core and System Mode...................................... 5-79
Exiting Low Power States-Core-Only Mode .................................................. 5-80
Exiting Low Power States-Core and System Mode........................................ 5-80
Power State Transitions from an ACPI Perspective .......................................... 5-81
MPC8313E Low Power Sequencing ................................................................. 5-85
PMC External Power Supply Control ............................................................... 5-90
Low-Power Considerations ............................................................................... 5-92
Arbiter and Bus Monitor
Title
Chapter 6
Page
Number
ix