Interrupt Event Register (Ievent) - Freescale Semiconductor MPC8313E Family Reference Manual

Enhanced Three-Speed Ethernet Controllers
Table 15-7 describes the field settings for TSEC_ID2[TSEC_INT].
15.5.3.1.3

Interrupt Event Register (IEVENT)

Interrupt events cause bits in the IEVENT register to be set. Software may poll this register at any time to
check for pending interrupts. If an event occurs and its corresponding enable bit is set in the interrupt mask
register (IMASK), the event also causes a hardware interrupt at the PIC. A bit in the interrupt event register
is cleared by writing a 1 to that bit position. A write of 0 has no effect.
Each eTSEC can issue three kinds of hardware interrupt to the PIC:
1. Transmit data frame interrupts—Issued whenever bits TXB or TXF of IEVENT are set to 1 and
either transmit interrupt coalescing is disabled or the interrupt coalescing thresholds have been met
for TXF. To negate this hardware interrupt, software must clear both TXB and TXF bits.
2. Receive data frame interrupts—Issued whenever bits RXB or RXF of IEVENT are set to 1 and
either receive interrupt coalescing is disabled or the interrupt coalescing thresholds have been met
for RXF. To negate this hardware interrupt, software must clear both RXB and RXF bits.
3. Error, diagnostic, and special interrupts—Issued whenever bits MAG, GTSC, GRSC, TXC, RXC,
BABR, BABT, LC, CRL, FGPI, FIR, FIQ, DPE, PERR, EBERR, TXE, XFUN, BSY, MSRO,
MMRD, or MMRW of IEVENT are set to 1. Software must clear all of these bits to negate an
error/diagnostic/special hardware interrupt.
— Magic Packet reception event is: MAG
— Operational diagnostics are events on: GTSC, GRSC, TXC, and RXC
— Interrupts resulting from errors/problems detected in the network or transceiver are: BABR,
BABT, LC, and CRL
— Interrupts resulting from internal or combination errors are: FIR, FIQ, DPE, PERR, EBERR,
TXE, XFUN, and BSY
— Special function interrupts are: FGPI, MSRO, MMRD, and MMRW
Some of the error interrupts are independently counted in the MIB block counters. Software may choose
to mask off these interrupts because these errors are visible to network management through the MIB
counters.
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
15-24
Table 15-7. TSEC_ID2[TSEC_INT] Field Settings
Bit
10 0 Ethernet mode not supported
1 Ethernet mode supported
11–13 Reserved
14 0 Can be configured to run in Ethernet normal/full mode
1 Ethernet normal/full mode off
15 0 Can be configured to run in Ethernet reduced mode
1 Ethernet reduced mode off
Mode
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