User-Programmable Machines (Upms) - Freescale Semiconductor MPC8313E Family Reference Manual

Powerquicc ii pro integrated processor

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Enhanced Local Bus Controller

6. The CPU now commences fetching instructions, in random order, from the FCM buffer RAM. This

first-level boot loader typically copies a secondary boot loader into system memory, and continues

booting from there. Boot software must clear FMR[BOOT] to enable normal operation of FCM.

User-Programmable Machines (UPMs)

UPMs are flexible interfaces that connect to a wide range of memory devices. At the heart of each UPM

is an internal RAM array that specifies the logical value driven on the external memory control signals

(LCSn, LBS[0:1] and LGPL[0:5]) for a given clock cycle. Each word in the RAM array provides bits that

allow a memory access to be controlled with a resolution of up to one quarter of the external bus clock

period on the byte-select and chip-select lines. A gap of 2 dead LCLK cycles is present on the UPM

interface between UPM transactions.

If the LGPL4/LGTA/LFRB/LUPWAIT signal is used as both an input and

an output, a weak pull-up is required. Refer to the hardware specification for

details regarding termination options.

Figure 10-58

shows the basic operation of each UPM.

Memory Access Request

(issued in software)

Exception Request

Figure 10-58. User-Programmable Machine Functional Block Diagram

The following events initiate a UPM cycle:

Any internal device requests an external memory access to an address space mapped to a

chip-select serviced by the UPM

A UPM refresh timer expires and requests a transaction, such as a DRAM refresh

A bus monitor time-out error during a normal UPM cycle redirects the UPM to execute an

exception sequence

MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3

Internal/External

Timer Request

Internal Controls

Freescale Semiconductor

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