Freescale Semiconductor MPC8313E Family Reference Manual page 148

Signal Descriptions
Table 3-1. MPC8313E Signal Reference by Functional Block (continued)
Name
SD_REF_CLK SerDes PLL
reference clock
(complement)
TXA Serial transmitter,
lane A, positive data
TXA Serial transmitter,
lane A, negative
data (complement)
TXB Serial transmitter,
lane B, positive data
TXB Serial transmitter,
lane B, negative
data (complement)
XCOREVDD[0:2] SerDes transceiver
core supply
XCOREVSS[0:2] SerDes transceiver
core ground
XPADVDD[0:1] SerDes transceiver
pad supply
XPADVSS[0:1] SerDes transceiver
pad ground
LAD[0:15] LBC address/data
LA[0:4] LBC port address
LA[5] LBC port address
LA[6:7] LBC port address
LA[8:9] LBC port address
LA[10:25] LBC port address
LCS[0:3] eLBC chip select
0–3
LWE0/LFWE0/LBS0 eLBC write enable
0/FCM write enable
0/UPM byte (lane)
select 0
LWE1/LFWE1/LBS1 eLBC write enable
1/FCM write enable
1/UPM byte (lane)
select 1
LBCTL eLBC data buffer
control
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
3-10
Functional
Description
Block
SGMII PHY
SGMII PHY
SGMII PHY
SGMII PHY
SGMII PHY
SGMII PHY
SGMII PHY
SGMII PHY
SGMII PHY
eLBC
eLBC
eLBC
eLBC
eLBC
eLBC
eLBC
eLBC
eLBC
eLBC
No. of Table/
I/O
Signals Page
1 I 15-2/15-8
1 O 15-2/15-8
1 O 15-2/15-8
1 O 15-2/15-8
1 O 15-2/15-8
2
3 PWR 15-2/15-8
3 GND 15-2/15-8
2
2 PWR 15-2/15-8
2 GND 15-2/15-8
16 I/O 10-2/10-5
5 I/O 10-2/10-5
1 I/O 10-2/10-5
2 I/O 10-2/10-5
2 I/O 10-2/10-5
16 O 10-2/10-5
4 O 10-2/10-5
1 O 10-2/10-5
1 O 10-2/10-5
1 O 10-2/10-5
Alternate Table/
Function(s) Page
SD_REF_CLK 15-2/15-8
TXA 15-2/15-8
TXA 15-2/15-8
TXB 15-2/15-8
TXB 15-2/15-8
— —
— —
— —
— —
— —
MSRCID[0:4]/ 9-1/9-3,
GPIO[0:4] 21-1/21-2
MDVAL/GPIO[5] 9-1/9-3,
21-1/21-2
GPIO[6:7] 21-1/21-2
GPIO1[13:14] 21-1/21-2
— —
— —
— —
— —
— —
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