Mdeu End-Of-Message Register (Mdeuemr); Mdeu Context Registers - Freescale Semiconductor MPC8313E Family Reference Manual

Security Engine (SEC) 2.2
0
Field
Reset
R/W
Addr

14.4.2.10 MDEU End-of-Message Register (MDEUEMR)

The end-of-message register in the MDEU (MDEUEMR), shown in
an authentication operation may be completed. After the final message block is written to the private
MDEU input FIFO, the MDEUEMR must be written. The value in the data size register will be used to
determine how many bits of the final message block (always 512) will be processed. Note that this register
has no data size, and during the write operation, the host data bus is not read. Hence, any data value is
accepted. Normally, a write operation with a zero data value is performed. Moreover, no read operation
from this register is meaningful, but no error is generated, and a zero value is always returned. Writing to
the MDEUEMR is merely a trigger causing the MDEU to process the final block of a message, allowing
it to signal DONE.
0
Field
Reset
R/W
Addr

14.4.2.11 MDEU Context Registers

In the MDEU, context consists of the hash plus the message length count. Write access to the MDEU
context register block allows continuation of a previous hash. Reading these registers provide the resulting
message digest or HMAC, along with an aggregate bit count.
SHA-1, SHA-224, and SHA-256 are big endian. MD5 is little endian. The
MDEU module internally reverses the endianness of the five registers A, B,
C, D, and E upon writing to or reading from the MDEU context if the
MDEU mode register indicates MD5 is the hash of choice. Most other
endian considerations are performed as 8-byte swaps. In this case, 4-byte
endianness swapping is performed within the A, B, C, D, and E fields as
individual registers. Reading this memory location while the module is not
done will generate an error interrupt.
After a power-on reset, all the MDEU context register values are cleared to 0.
MDEU context registers are initialized if the INIT bit is set in the MDEU mode register. All registers are
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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Figure 14-23. MDEU ICV Size Register
Figure 14-24. MDEU End-of-Message Register (MDEUEMR)
0
R/W
MDEU 0x3_6040
Figure
MDEU End-of-Message
0
W
MDEU 0x3_6050
NOTE
56 57
ICV_Size
14-24, is used to indicate that
Figure 14-25 shows how the
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