Stop Bit; Baud-Rate Generator Logic; Local Loopback Mode - Freescale Semiconductor MPC8313E Family Reference Manual

DUART
transferring data. When receiving data, a parity error can occur if an unexpected parity value is detected
(see Section 18.3.1.10, "Line Status Registers (ULSR1 and
18.4.1.4

STOP Bit

The transmitter device ends the write transfer by generating a STOP bit. The STOP bit is always high. The
user can program the length of the STOP bit(s) in the ULCR. Both the receiver and transmitter STOP bit
length must agree before attempting to transfer data. A framing error can occur if an invalid STOP bit is
detected.
18.4.2

Baud-Rate Generator Logic

Each UART contains an independent programmable baud-rate generator, that is capable of taking the
system clock input and dividing the input by any divisor from 1 to 2
The baud rate is defined as the number of bits per second that can be sent over the UART bus. The formula
for calculating baud rate is as follows:
Baud rate = (1/16) × (system clock frequency/divisor value)
Therefore, the output frequency of the baud-rate generator is 16 times the baud rate.
The divisor value is determined by the following two 8-bit registers to form a 16-bit binary number:
• UART divisor most significant byte register (UDMB)
• UART divisor least significant byte register (UDLB)
Upon loading either of the divisor latches, a 16-bit baud-rate counter is loaded.
The divisor latches must be loaded during initialization to ensure proper operation of the baud-rate
generator. Both UART devices on the same bus must be programmed for the same baud rate before starting
a transfer.
The baud clock can be passed to the performance monitor by enabling UAFR[BO]. This can be used to
determine baud-rate errors.
18.4.3

Local Loopback Mode

Local loopback mode is provided for diagnostic testing. The data written to UTHR can be read from the
receiver buffer register (URBR) of the same UART. In this mode, the MODEM control register
UMCR[RTS] is internally tied to the MODEM status register UMSR[CTS]. The transmitter SOUT is set
to a logic 1 and the receiver SIN is disconnected. The output of the transmitter shift register is looped back
into the receiver shift register input. The CTS (input signal) is disconnected, RTS is internally connected
to CTS, and the RTS (output signal) becomes inactive. In this diagnostic mode, data that is transmitted is
immediately received. In local loopback mode the transmit and receive data paths of the DUART can be
verified. Note that in local loopback mode, the transmit/receive interrupts are fully operational and can be
controlled by the interrupt enable register (UIER).
MPC8313E PowerQUICC II Pro Integrated Processor Family Reference Manual, Rev. 3
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ULSR2)").
16
– 1.
Freescale Semiconductor