Analog Devices ADSP-BF53x Blackfin Reference page 532

Instruction Overview
The division can either be signed or unsigned, but the dividend and divi-
sor must both be of the same type. The divisor cannot be negative. A
signed division operation, where the dividend may be negative, begins the
sequence with the
execution of the
sion omits the
the flag of the
AQ
Up to 16 bits of signed quotient resolution can be calculated by issuing
once, then repeating the
DIVS
unsigned quotient is calculated by omitting
issuing 16
DIVQ
Less quotient resolution is produced by executing fewer
The result of each successive addition or subtraction appears in
dividend_register
step. The contents of
instruction.
The final quotient appears in the low-order half-word of
dividend_register
computes the sign bit of the quotient based on the signs of the divi-
DIVS
dend and divisor.
initializes the dividend for the first addition or subtraction.
no addition or subtraction.
either adds (dividend + divisor) or subtracts (dividend – divisor)
DIVQ
based on the
AQ
iteration. If
AQ
performed.
See "Flags Affected" on page 15-4
flag.
AQ
15-20 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
("divide-sign") instruction, followed by repeated
DIVS
("divide-quotient") instruction. An unsigned divi-
DIVQ
instruction. In that case, the user must manually clear
DIVS
register before issuing the
ASTAT
DIVQ
instructions.
, aligned and ready for the next addition or subtraction
divisor_register
at the end of the successive add/subtract sequence.
initializes the
DIVS
flag, then reinitializes the
is 1, addition is performed; if
DIVQ
instruction 15 times. A 16-bit
, clearing the
DIVS
are not modified by this
flag based on that sign, and
AQ
flag and dividend for the next
AQ
is 0, subtraction is
AQ
for the conditions that set and clear the
instructions.
flag, then
AQ
iterations.
DIVQ
performs
DIVS