Analog Devices ADSP-BF53x Blackfin Reference page 989

Table C-23. 32-Bit Opcode Instructions (Sheet 36 of 40)
Instruction
and Version
Logical Shift
Dreg_hi = Dreg_lo >> uimm4
Logical Shift
Dreg_hi = Dreg_hi << uimm4
Logical Shift
Dreg_hi = Dreg_hi >> uimm4
Vector Arithmetic Shift
Dreg = Dreg >>> uimm5 (V)
Vector Arithmetic Shift
Dreg = Dreg << uimm5 (V, S)
Vector Logical Shift
Dreg = Dreg << uimm4 (V)
Vector Logical Shift
Dreg = Dreg >> uimm4 (V)
Arithmetic Shift
Dreg = Dreg >>> uimm5
Arithmetic Shift
Dreg = Dreg << uimm5 (S)
Logical Shift
Dreg = Dreg << uimm5
Logical Shift
Dreg = Dreg >> uimm5
Rotate
Dreg = ROT Dreg BY imm6
Arithmetic Shift
A0 = A0 >>> uimm5
Arithmetic Shift
A1 = A1 >>> uimm5
Logical Shift
A0 = A0 << uimm5
Logical Shift
A0 = A0 >> uimm5
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Instruction Opcodes
Opcode
Range
0xC680 A180—
0xC680 AFFF
0xC680 B000—
0xC680 BE7F
0xC680 B180—
0xC680 BFFF
0xC681 0100—
0xC681 0FFF
0xC681 4000—
0xC681 4EFF
0xC681 8000—
0xC681 8E7F
0xC681 8180—
0xC681 8FFF
0xC682 0100—
0xC682 0FFF
0xC682 4000—
0xC680 4EFF
0xC682 8000—
0xC682 8EFF
0xC682 8100—
0xC682 8FFF
0xC682 C000—
0xC682 CFFF
0xC683 0100—
0xC683 01F8
0xC683 1100—
0xC683 11F8
0xC683 4000—
0xC683 40F8
0xC683 4100—
0xC683 41F8
C-189