Analog Devices ADSP-BF53x Blackfin Reference page 835

Table C-11. Move Instructions (Sheet 8 of 9)
Instruction
and Version
Move Register Half
Dreg_hi = A1 (T)
Move Register Half
Dreg_hi = A1 (S2RND)
Move Register Half
Dreg_hi = A1 (ISS2)
Move Register Half
Dreg_hi = A1 (IH)
Move Register Half
Dreg_lo = A0, Dreg_hi = A1
Dreg_hi = A1, Dreg_lo = A0
Move Register Half
Dreg_lo = A0, Dreg_hi = A1 (FU)
Dreg_hi = A1, Dreg_lo = A0 (FU)
Move Register Half
Dreg_lo = A0, Dreg_hi = A1 (IS)
Dreg_hi = A1, Dreg_lo = A0 (IS)
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0xC047 1800— 1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 1
0xC047 19C0
0 0 0 1 1 0 0
0xC027 1800— 1 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1
0xC027 19C0
0 0 0 1 1 0 0
0xC127 1800— 1 1 0 0 0 0 0 1 0 0 1 0 0 1 1 1
0xC127 19C0
0 0 0 1 1 0 0
0xC167 1800— 1 1 0 0 0 0 0 1 0 1 1 0 0 1 1 1
0xC167 19C0
0 0 0 1 1 0 0
0xC007 3800— 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1
0xC007 39C0
0 0 1 1 1 0 0
0xC087 3800— 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1
0xC087 39C0
0 0 1 1 1 0 0
0xC107 3800— 1 1 0 0 0 0 0 1 0 0 0 0 0 1 1 1
0xC107 39C0
0 0 1 1 1 0 0
Instruction Opcodes
Bin
Dreg # 0 0 0 0 0 0
Dreg # 0 0 0 0 0 0
Dreg # 0 0 0 0 0 0
Dreg # 0 0 0 0 0 0
Dreg # 0 0 0 0 0 0
Dreg # 0 0 0 0 0 0
Dreg # 0 0 0 0 0 0
C-35