Analog Devices ADSP-BF53x Blackfin Reference page 808

Introduction
Core Register Encoding Map
Instruction opcodes can address any core register by Register Group and
Register Number using the following encoding.
Table C-4. Core Register Encoding Map
REGISTER
GROUP 0
0 R0
1 P0
2 I0
3 B0
4 A0.x
5 <res.>
6 LC0
7 USP
Opcode Representation
The Blackfin architecture accepts 16- and 32-bit opcodes. This document
represents the opcodes as hexadecimal values or ranges of values and as
binary bit fields.
Some instructions have no variable arguments, and therefore produce only
one hex value. The value appears in the "min" Hex Opcode Range col-
umn. Instructions that support variable arguments (such as a choice of
source or destination registers, optional modes, or constants) span a range
of hex values. The minimum and maximum allowable hex values are
shown in that case. As explained in
page C-10, the instruction may not produce all possible hex values within
the range.
C-8 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
REGISTER NUMBER
1 2
R1 R2
P1 P2
I1 I2
B1 B2
A0.w A1.x
<res.> <res.>
LT0 LB0
SEQSTAT SYSCFG RETI RETX RETN
"Holes In Opcode Ranges" on
3 4 5
R3 R4 R5
P3 P4 P5
I3 M0 M1
B3 L0 L1
A1.w <res.> <res.>
<res.> <res.> <res.>
LC1 LT1 LB1
6 7
R6 R7
SP FP
M2 M3
L2 L3
ASTAT RETS
<res.> <res.>
CYCLES CYCLES2
RETE EMUDAT