Analog Devices ADSP-BF53x Blackfin Reference page 396

Instruction Overview
Accumulator to Half D-register Moves
Dreg_lo = A0 (opt_mode) ; /* move A0 to lower half of Dreg (b) */
Dreg_hi = A1 (opt_mode) ;
*/
Dreg_lo = A0, Dreg_hi = A1 (opt_mode) ; /* move both values at
once; must go to the lower and upper halves of the same Dreg (b)
*/
Dreg_hi = A1, Dreg_lo = AO (opt_mode) ;
once; must go to the upper and lower halves of the same Dreg (b)
*/
Syntax Terminology
:
Dreg_lo R7–0.L
:
Dreg_hi R7–0.H
: the least significant 16 bits of Accumulator
A0.L
: the least significant 16 bits of Accumulator
A1.L
: the most significant 16 bits of Accumulator
A0.H
: the most significant 16 bits of Accumulator
A1.H
: Optionally
opt_mode
Table 9-2 on page
Instruction Length
In the syntax, comment (b) identifies 32-bit instruction length.
9-16 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
/* move A1 to upper half of Dreg (b)
, ,
(FU) (IS) (IU)
9-19).
/* move both values at
A0.W
A1.W
A0.W
A1.W
, , ,
(T) (S2RND) (ISS2)
, or (See
(IH)