Analog Devices ADSP-BF53x Blackfin Reference page 502

Instruction Overview
Four versions of the Logical Shift instruction support pointer shifting.
The instruction does not implicitly modify the input
the P-register versions of this instruction,
P-register as
src_pntr
The rest of this description applies to the data shift versions of this
instruction relating to D-registers and Accumulators.
The Logical Shift instruction supports 16-bit and 32-bit instruction
length.
• The "
>>=
ing for smaller code at the expense of flexibility.
• The "
>>
length, providing a separate source and destination register, alter-
native data sizes, and parallel issue with Load/Store instructions.
Both syntaxes support constant and registered shift magnitudes.
Table 14-2. Logical Shifts
Syntax
">>="
and "<<="
">>", "<<",
and "LSHIFT"
For the
LSHIFT
direction of the shift.
• Positive shift magnitudes produce Left shifts.
• Negative shift magnitudes produce Right shifts.
14-16 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
. Doing so explicitly modifies the source register.
" and " " syntax instruction is 16 bits in length, allow-
<<=
", " ", and "
<< LSHIFT
Description
The value in dest_reg is shifted by the number of places specified by
shift_magnitude. The data size is always 32 bits long. The entire 32 bits
of the shift_magnitude determine the shift value. Shift magnitudes larger
than 0x1F produce a 0x00000000 result.
The value in src_reg is shifted by the number of places specified in
shift_magnitude, and the result is stored into dest_reg.
The LSHIFT versions can shift 32-bit Dreg and 40-bit Accumulator reg-
isters by up to –32 through +31 places.
version, the sign of the shift magnitude determines the
can be the same
dest_pntr
" syntax instruction is 32 bits in
value. For
src_pntr