Analog Devices ADSP-BF53x Blackfin Reference page 932

Vector Operations Instructions
Table C-21. Vector Operations Instructions (Sheet 26 of 33)
Instruction
and Version
Vector Multiply and
Multiply-Accumulate
A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = (A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi)
Vector Multiply and
Multiply-Accumulate
A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = (A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi) (FU)
Vector Multiply and
Multiply-Accumulate
A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi ,
Dreg_hi = (A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi) (IS)
Vector Multiply and
Multiply-Accumulate
Dreg_lo = (A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi) ,
A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi
Vector Multiply and
Multiply-Accumulate
Dreg_lo = (A0 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi) ,
A1 {=, +=, or –=} Dreg_lo_hi * Dreg_lo_hi (FU)
C-132 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Opcode
Range 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 0 0 0 0 0 0 0 0 1 op1
0xC004 0000—
0xC007 DFFF Dreg
half 1 0 op0
1 1 0 0 0 0 0 0 1 0 0 0 0 1 op1
0xC084 0000—
0xC087 DFFF Dreg
half 1 0 op0
1 1 0 0 0 0 0 1 0 0 0 0 0 1 op1
0xC104 0000—
0xC107 DFFF Dreg
half 1 0 op0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 op1
0xC000 2000—
0xC003 FFFF Dreg
half 1 1 op0
1 1 0 0 0 0 0 0 1 0 0 0 0 0 op1
0xC080 2000—
0xC083 FFFF Dreg
half 1 1 op0
Bin
Dreg Dest. src_reg_
half 0 Dreg # 0 Dreg #
Dreg Dest. src_reg_
half 0 Dreg # 0 Dreg #
Dreg Dest. src_reg_
half 0 Dreg # 0 Dreg #
Dreg Dest. src_reg_
half 0 Dreg # 0 Dreg #
Dreg Dest. src_reg_
half 0 Dreg # 0 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #
src_reg_
1 Dreg #