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Data Memory Control Register (DMEM_CONTROL)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0xFFE0 0004
15 14 13 12 11 10
PORT_PREF1 (DAG1 Port
Preference)
0 - DAG1 non-cacheable fetches
use port A
1 - DAG1 non-cacheable fetches
use port B
PORT_PREF0 (DAG0 Port
Preference)
0 - DAG0 non-cacheable fetches
use port A
1 - DAG0 non-cacheable fetches
use port B
DCBS (L1 Data Cache Bank Select)
Valid only when DMC[1:0] = 11. Determines
whether Address bit A[14] or A[23] is used to
select the L1 data cache bank.
0 - Address bit 14 is used to select Bank A or B
for cache access. If bit 14 of address is 1,
select L1 Data Memory Data Bank A; if bit 14
of address is 0, select L1 Data Memory Data
Bank B.
1 - Address bit 23 is used to select Bank A or B for
cache access. If bit 23 of address is 1, select
L1 Data Memory Data Bank A; if bit 23 of
address is 0, select L1 Data Memory Data
Bank B.
See
"Example of Mapping Cacheable Address
Space" on page
6-30.
Figure 6-9. L1 Data Memory Control Register
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
0
0
0
0
0
0
0
0
9
8
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
Memory
Reset = 0x0000 1001
ENDCPLB (Data Cacheability
Protection Lookaside Buffer
Enable)
0 - CPLBs disabled. Minimal
address checking only
1 - CPLBs enabled
DMC[1:0] (L1 Data Memory
Configure)
See the Blackfin Processor
Hardware Reference for infor-
mation specific to your part
6-25
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