Table of Contents
Advertisement
Memory
dirty or modified. A state bit, stored along with the tag, indicating
whether the data in the data cache line has been changed since it was cop-
ied from the source memory and, therefore, needs to be updated in that
source memory.
exclusive, clean. The state of a data cache line, indicating that the line is
valid and that the data contained in the line matches that in the source
memory. The data in a clean cache line does not need to be written to
source memory before it is replaced.
fully associative. Cache architecture in which each line can be placed any-
where in the cache.
index. Address portion that is used to select an array element (for example,
a line index).
invalid. Describes the state of a cache line. When a cache line is invalid, a
cache line match cannot occur.
least recently used (LRU) algorithm. Replacement algorithm, used by
cache, that first replaces lines that have been unused for the longest time.
Level 1 (L1) memory. Memory that is directly accessed by the core with
no intervening memory subsystems between it and the core.
little endian. The native data store format of the Blackfin processor.
Words and half words are stored in memory (and registers) with the least
significant byte at the lowest byte address and the most significant byte in
the highest byte address of the data storage location.
replacement policy. The function used by the processor to determine
which line to replace on a cache miss. Often, an LRU algorithm is
employed.
set. A group of N-line storage locations in the Ways of an N-Way cache,
selected by the
field of the address (see
Figure 6-4 on page
6-12).
INDEX
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
6-75
Advertisement
Table of Contents
