Analog Devices ADSP-BF53x Blackfin Reference page 673

Table 18-25. Destination Registers Receive
dest_reg_0:
dest_reg_1:
The only valid input source register pairs are
The Quad 8-Bit Subtract instruction provides byte alignment directly in
the source register pairs
and .
I0 I1
• The two LSBs of the
source register pair
• The two LSBs of the
source register pair
The relationship between the I-register bits and the byte alignment is
illustrated shown in
In the default source order case (for example, not the (R) syntax), assume a
source register pair contains the data shown in
Table 18-26. I-register Bits and the Byte Alignment
The bytes selected are
Two LSB's of I0 or I1
00b:
01b:
10b:
11b:
This instruction prevents exceptions that would otherwise be caused by
misaligned 32-bit memory loads issued in parallel.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
31................24 23................16
y1 - z1
y3 - z3
src_reg_0
register determine the byte alignment for
I0
src_reg_0
register determine the byte alignment for
I1
src_reg_1
Table 18-26.
src_reg_pair_HI
byte7 byte6
byte6
Video Pixel Operations
15..................8
and
R1:0
and based on index registers
src_reg_1
(typically ).
R1:0
(typically ).
R3:2
Table
src_reg_pair_LO
byte5 byte4 byte3
byte3
byte4 byte3
byte5 byte4 byte3
byte5 byte4 byte3
7....................0
y0 - z0
y2 - z2
.
R3:2
18-26.
byte2 byte1 byte0
byte2 byte1 byte0
byte2 byte1
byte2
18-33