Analog Devices ADSP-BF53x Blackfin Reference page 342

Instruction Overview
Parallel Issue
The 16-bit versions of this instruction can be issued in parallel with spe-
cific other instructions.
Instructions" on page 20-1.
The 32-bit versions of this instruction cannot be issued in parallel with
other instructions.
Example
r3 = w [ p0 ] (z) ;
r7 = w [ p1 ++ ] (z) ;
r2 = w [ sp -- ] (z) ;
r6 = w [ p2 + 12 ] (z) ;
r0 = w [ p4 + 0x8004 ] (z) ;
r1 = w [ p0 ++ p1 ] (z) ;
Also See
Load Half-Word –
High Data Register
Special Applications
To read consecutive, aligned 16-bit values for high-performance DSP
operations, use the Load Data Register instructions instead of these
Half-Word instructions. The Half-Word Load instructions use only half
the available 32-bit data bus bandwidth, possibly imposing a bottleneck
constriction in the data flow rate.
8-18 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
For more information, see "Issuing Parallel
Sign-Extended, Load Low Data Register
Half, Load Data Register
Half, Load