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Hardware Errors and Exception Handling
Table 4-11. Events That Cause Exceptions (Cont'd)
Exception
Data access mis-
aligned address viola-
tion
Unrecoverable event
Data access CPLB
miss
Data access multiple
CPLB hits
Exception caused by
an emulation watch-
point match
Instruction fetch mis-
aligned address viola-
tion
Instruction fetch
CPLB protection vio-
lation
Instruction fetch
CPLB miss
4-64
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
EXCAUSE
Type:
[5:0]
(E) Error
(S) Service
See note 1.
0x24
E
0x25
E
0x26
E
0x27
E
0x28
E
0x2A
E
0x2B
E
0x2C
E
Notes/Examples
Attempted misaligned data memory or
data cache access.
For example, an exception generated while
processing a previous exception.
Used by the MMU to signal a CPLB miss
on a data access.
More than one CPLB entry matches data
fetch address.
There is a watchpoint match, and one of
the EMUSW bits in the Watchpoint
Instruction Address Control register
(WPIACTL) is set.
Attempted misaligned instruction cache
fetch. On a misaligned instruction fetch
exception, the return address provided in
RETX is the destination address which is
misaligned, rather than the address of the
offending instruction. For example, if an
indirect branch to a misaligned address
held in P0 is attempted, the return address
in RETX is equal to P0, rather than to the
address of the branch instruction. (Note
this exception can never be generated
from PC-relative branches, only from
indirect branches.)
Illegal instruction fetch access (memory
protection violation).
CPLB miss on an instruction fetch.
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