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Instruction Overview
Instruction Length
In the syntax, comment (a) identifies 16-bit instruction length. Comment
(b) identifies 32-bit instruction length.
Functional Description
The Load Half-Word – Zero-Extended instruction loads 16 bits from a
memory location into the lower half of a 32-bit data register. The instruc-
tion zero-extends the upper half of the register. The Pointer register is a
P-register.
The indirect address and offset must yield an even numbered address to
maintain 2-byte half-word address alignment. Failure to maintain proper
alignment causes a misaligned memory access exception.
Options
The Load Half-Word – Zero-Extended instruction supports the following
options.
• Post-increment the source pointer by 2 bytes.
• Post-decrement the source pointer by 2 bytes.
• Offset the source pointer with a small (5-bit), half-word-aligned
(even), unsigned constant.
• Offset the source pointer with a large (17-bit), half-word-aligned
(even), signed constant.
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ADSP-BF53x/BF56x Blackfin Processor Programming Reference
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