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Data Test Registers
Data Test Command Register (DTEST_COMMAND)
0xFFE0 0300
Access Way/Instruction
Address Bit 11
0 - Access Way0/Instruction bit 11 = 0
1 - Access Way1/Instruction bit 11 = 1
Data/Instruction Access
0 - Access Data
1 - Access Instruction
Data Bank Access
See the Blackfin Processor
Hardware Reference for infor-
mation specific to your part
Data Cache Select/
Address Bit 14
0 - Reserved/Instruction bit 14 = 0
1 - Select Data Cache Bank/Instruction bit 14 = 1
Set Index[5:0]
Selects one of 64 sets
Double Word Index[1:0]
Selects one of four 64-bit
double words in a 256-bit line
Figure 6-13. Data Test Command Register
6-40
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X
X
X
X
X
X
X
X
15 14 13 12 11 10
9
8
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
Reset = Undefined
Subbank Access[1:0]
(SRAM ADDR[13:12])
00 - Access subbank 0
01 - Access subbank 1
10 - Access subbank 2
11 - Access subbank 3
Read/Write Access
0 - Read access
1 - Write access
Array Access
0 - Access tag array
1 - Access data array
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