Analog Devices ADSP-BF53x Blackfin Reference page 1017

ICPLB_FAULT_ADDR (ICPLB fault
address) register, 6-63
ICPLB_STATUS (ICPLB status) register,
6-61, 6-62
identifying processor mode,
IDLE (idle) instruction, 3-9, 16-3, 16-14,
16-16, A-1, C-99
idle state
defined, 3-9
processor mode, 3-2
program flow, 4-2
transition to, 3-10
wake up core from, 4-34
IF1 (instruction fetch 1),
IF2 (instruction fetch 2),
IF3 (instruction fetch 3),
IF3 stage, 4-9
IF CC instruction, 9-8
IF CC JUMP instruction,
I-fetch access exception,
I-fetch CPLB miss, 4-65
I-fetch misaligned access,
I-fetch multiple CPLB hits,
I-fetch protection violation,
IFLUSH (instruction cache flush)
instruction, 6-6, 6-18, 17-9,
ILAT (core interrupt latch) register
diagram
EXCPT instruction,
latched interrupt request,
system interrupt processing,
illegal combination, exception type,
illegal use protected resource,
ILOC[3:0] (cache way lock) field, 6-5, 6-7,
6-17
IMASK (core interrupt mask) register,
4-31, 6-74
IMC (L1 instruction memory
configuration) bit, 6-6, 6-7,
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
3-2
4-7
4-7
4-7
7-5
4-65
4-65
4-65
4-65
C-101
16-20
4-39
4-31
4-66
4-66
6-19
IMEM_CONTROL (instruction memory
control) register, 6-5,
imm16 constant, 8-4
imm3 constant, 11-6
imm6 constant, 14-21
imm7 constant, 8-4, 15-16
immediate constant, C-5
immediate shift
defined, 2-50
example, 2-49, 2-51
immediate values, designation,
implementation[15:0] field,
index, definition, 6-75
indexed addressing
example, 5-8
with immediate offset,
index registers (I[3:0])
add immediate instructions,
addresses, 5-8
defined, 1-14, 5-12
description, 1-21, C-3
example, 5-3
function in circular addressing,
load data register, 8-10
load high data register half, 8-23,
modify – decrement instructions,
modify – increment instructions,
store data register, 8-40
store high data register half,
store low data register half,
subtract immediate instruction,
indirect branch address,
initialization
loop registers, 7-15
of data address registers,
of interrupts, 4-34
of length registers, 5-4
inner loops, 4-25
input/output loop performance,
inputs and outputs (ALU),
Index
6-47
1-11
21-27
5-10
15-16
1-21
8-27
15-34
15-37
8-45
8-49
15-90
4-11
5-4
1-21
2-26
I-15