Swrst Register - Analog Devices ADSP-BF53x Blackfin Reference

After either the watchdog or System Software reset is initiated, the proces-
sor ensures that all asynchronous peripherals have recognized and
completed a reset.
For a reset generated by the watchdog timer, the processors transitions
into the Boot mode sequence. The Boot mode is configured by the state of
the and the No Boot on Software Reset control bits.
BMODE
If the No Boot on Software Reset bit in
sequence is determined by the

SWRST Register

A software reset can be initiated by setting the System Software Reset field
in the Software Reset register (
reset has occurred since the last time
respectively, indicate whether the Software Watchdog Timer or a Core
Double Fault has generated a software reset. Bits [15:13] are read-only
and cleared when the register is read. Bits [3:0] are read/write.
When the
BMODE
Reset bit in
SYSCR
on-chip L1 memory. In this configuration, the core begins fetching
instructions from the beginning of on-chip L1 memory.
When the
BMODE
from address 0x2000 0000 (the beginning of ASYNC Bank 0).
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
BMODE
SWRST
pins are not set to b#00 and the No Boot on Software
is set, the processor starts executing from the start of
pins are set to b#00 the core begins fetching instructions
Operating Modes and States
is cleared, the reset
SYSCR
control bits.
). Bit 15 indicates whether a software
was read. Bit 14 and Bit 13,
SWRST
3-15