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L1 Instruction Memory
L1 Instruction Memory consists of a combination of dedicated SRAM and
banks which can be configured as SRAM or cache. For the 16K byte bank
that can be either cache or SRAM, control bits in the
ter can be used to organize all four subbanks of the L1 Instruction
Memory as:
• A simple SRAM
• A 4-Way, set associative instruction cache
• A cache with as many as four locked Ways
L1 Instruction Memory can be used only to store instructions.
IMEM_CONTROL Register
The Instruction Memory Control register (
trol bits for the L1 Instruction Memory. By default after reset, cache and
Cacheability Protection Lookaside Buffer (CPLB) address checking is dis-
abled (see
"L1 Instruction Cache" on page
When the
LRUPRIORST
bits (see
"ICPLB_DATAx Registers" on page
simultaneously forces all cached lines to be of equal (low) importance.
Cache replacement policy is based first on line importance indicated by
the cached states of the
recently used). See
complete details. This bit must be 0 to allow the state of the
bits to be stored when new lines are cached.
The
ILOC[3:0]
ually loaded into cache. See
6-17. These bits specify which Ways to remove from the cache replace-
ment policy. This has the effect of locking code present in
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
bit is set to 1, the cached states of all
CPLB_LRUPRIO
"Instruction Cache Locking by Line" on page 6-16
bits provide a useful feature only after code has been man-
"Instruction Cache Locking by Way" on page
IMEM_CONTROL
IMEM_CONTROL
6-10).
6-55) are cleared. This
bits, and then on LRU (least
Memory
regis-
) contains con-
CPLB_LRUPRIO
for
CPLB_LRUPRIO
6-5
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